公开(公告)号：US07629244B2

公开(公告)日：2009-12-08

申请号：US11491281

申请日：2006-07-24

申请人： Soo-doo Chae ,  Chung-woo Kim ,  Ju-hyung Kim

发明人： Soo-doo Chae ,  Chung-woo Kim ,  Ju-hyung Kim

IPC分类号： H01L21/4763

CPC分类号： B82Y10/00 ,  H01L29/7888 ,  Y10S977/937 ,  Y10S977/938

摘要： A single electron transistor having a memory function and a fabrication method thereof are disclosed. In the single electron transistor, a first substrate and an insulation film are sequentially stacked, a second substrate is stacked on the insulation film and includes a source region, a channel region, and a drain region, a tunneling film is formed on the second substrate, at least two trap layers are formed on the tunneling film and are separated by an interval such that at least one quantum dot may be formed in a same interval in the channel region, and a gate electrode is formed to contact the at least two trap layers and the tunneling film between the at least two trap layers. Because the single electron transistor is simple and includes a single gate electrode, a fabricating process and an operational circuit thereof may be simplified, and power consumption may be reduced.

摘要翻译： 公开了具有记忆功能的单电子晶体管及其制造方法。 在单电子晶体管中，第一衬底和绝缘膜依次层叠，第二衬底层叠在绝缘膜上，并且包括源极区域，沟道区域和漏极区域，在第二衬底上形成隧穿膜 在隧道膜上形成至少两个陷阱层，并且以间隔隔开，使得至少一个量子点可以在沟道区域中以相同的间隔形成，并且形成栅电极以接触至少两个陷阱 层和至少两个陷阱层之间的隧道膜。 由于单电子晶体管简单并且包括单个栅极电极，所以可以简化制造工艺及其操作电路，并且可以降低功耗。

公开(公告)号：US07531870B2

公开(公告)日：2009-05-12

申请号：US11878277

申请日：2007-07-23

申请人： Ju-hyung Kim ,  Chung-woo Kim ,  Soo-doo Chae ,  Youn-seok Jeong

发明人： Ju-hyung Kim ,  Chung-woo Kim ,  Soo-doo Chae ,  Youn-seok Jeong

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7887

摘要： A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.

摘要翻译： 氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件包括在半导体衬底上包括具有SONOS结构的栅极的存储器型晶体管。 栅极通过依次层叠隧道氧化物层，存储器结构结构，其包括具有纳米级陷阱元件的陷阱位置，其中通过隧道氧化物层的电荷被捕获，以及栅极电极。 纳米尺寸的阱元件可以是由彼此分离以捕获电荷的纳米晶体组成的晶体层。 存储器节点结构可以包括与纳米级陷阱元件隔离的附加存储器节点层。

公开(公告)号：US20080261366A1

公开(公告)日：2008-10-23

申请号：US12125280

申请日：2008-05-22

申请人： Sang-hun JEON ,  Chung-woo Kim

发明人： Sang-hun JEON ,  Chung-woo Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile memory device having an improved erase efficiency and a method of manufacturing the same are provided. The method includes: forming a stack structure of a tunnel dielectric layer, a charge trapping layer, a charge blocking layer and a gate on a semiconductor substrate; and performing a post treatment of the gate using an oxygen or CF4 plasma or ion implantation to increase a work function of an element forming the gate. Since the work function of the metal layer forming the gate can be further increased, an electron back tunneling can be suppressed during an erase operation.

摘要翻译： 提供了具有改进的擦除效率的非易失性存储器件及其制造方法。 该方法包括：在半导体衬底上形成隧道介电层，电荷俘获层，电荷阻挡层和栅极的堆叠结构; 以及使用氧或CF 4等离子体或离子注入来执行栅极的后处理以增加形成栅极的元件的功函数。 由于可以进一步增加形成栅极的金属层的功函数，所以可以在擦除操作期间抑制电子反向隧穿。

公开(公告)号：US20080212376A1

公开(公告)日：2008-09-04

申请号：US12025372

申请日：2008-02-04

申请人： Yoon-dong Park ,  Jo-won Lee ,  Chung-woo Kim ,  Eun-hong Lee ,  Sun-ae Seo ,  Woo-joo Kim ,  Hee-soon Chae ,  Soo-doo Chae ,  I-hun Song

发明人： Yoon-dong Park ,  Jo-won Lee ,  Chung-woo Kim ,  Eun-hong Lee ,  Sun-ae Seo ,  Woo-joo Kim ,  Hee-soon Chae ,  Soo-doo Chae ,  I-hun Song

IPC分类号： G11C16/06 ,  H01L21/336 ,  G11C7/00

CPC分类号： G11C11/5621 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11551

摘要： Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.

摘要翻译： 提供了一种互补的非易失性存储器件，其操作和制造方法，逻辑器件和具有该非易失性存储器件的半导体器件及其读取电路。 互补非易失性存储器件包括顺序堆叠并具有互补关系的第一非易失性存储器和第二非易失性存储器。 第一和第二非易失性存储器被布置成使得其上表面相邻。

公开(公告)号：US20080157186A1

公开(公告)日：2008-07-03

申请号：US11980352

申请日：2007-10-31

申请人： Wan-jun Park ,  Jo-won Lee ,  Sang-hun Jeon ,  Chung-woo Kim

发明人： Wan-jun Park ,  Jo-won Lee ,  Sang-hun Jeon ,  Chung-woo Kim

IPC分类号： H01L29/792

CPC分类号： H01L21/28273 ,  H01L21/28282

摘要： A non-volatile memory device including a metal-insulator transition (MIT) material is provided. The non-volatile memory device includes a gate stack having a tunneling layer, a charge trap layer, a blocking layer and a gate electrode formed on a substrate, wherein at least one of the tunneling layer and the blocking layer is formed of an MIT (metal-insulator transition) material.

摘要翻译： 提供了包括金属 - 绝缘体转变（MIT）材料的非易失性存储器件。 非易失性存储器件包括具有隧道层，电荷陷阱层，形成在衬底上的阻挡层和栅电极的栅极堆叠，其中隧道层和阻挡层中的至少一个由MIT形成 金属 - 绝缘体转变）材料。

公开(公告)号：US07202521B2

公开(公告)日：2007-04-10

申请号：US10961481

申请日：2004-10-12

申请人： Moon-kyung Kim ,  Chung-woo Kim ,  Jo-won Lee ,  Eun-hong Lee ,  Hee-soon Chae

发明人： Moon-kyung Kim ,  Chung-woo Kim ,  Jo-won Lee ,  Eun-hong Lee ,  Hee-soon Chae

IPC分类号： H01L29/76

CPC分类号： G11C16/0475 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device, and methods of manufacturing and operating the same, the SONOS memory device includes a semiconductor layer including source and drain regions and a channel region, an upper stack structure formed on the semiconductor layer, the upper stack structure and the semiconductor layer forming an upper SONOS memory device, and a lower stack structure formed under the semiconductor layer, the lower stack structure and the semiconductor layer forming a lower SONOS memory device.

摘要翻译： 在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件及其制造和操作方法中，SONOS存储器件包括包括源极和漏极区域以及沟道区域的半导体层，上部堆叠结构形成在 半导体层，上层堆叠结构和形成上SONOS存储器件的半导体层，以及形成在半导体层下的下堆叠结构，下堆叠结构和半导体层形成下SONOS存储器件。

公开(公告)号：US20060180853A1

公开(公告)日：2006-08-17

申请号：US11200153

申请日：2005-08-10

申请人： Won-il Ryu ,  Jo-won Lee ,  Se-wook Yoon ,  Chung-woo Kim

发明人： Won-il Ryu ,  Jo-won Lee ,  Se-wook Yoon ,  Chung-woo Kim

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7923

摘要： In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region, and a channel region, a first side gate stack formed at a first side of the channel region, and a second side gate stack formed at a second side of the channel region opposite the first side of the channel region. In the SONOS memory device, at least two bits of data may be stored in each SONOS memory device, thereby allowing the integration density of the semiconductor memory device to be increased without increasing an area thereof.

摘要翻译： 在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件及其制造方法中，SONOS存储器件包括半导体衬底，沉积在半导体衬底上的绝缘层，形成在预定区域上的有源层 并且被分成源区域，漏极区域和沟道区域，形成在沟道区域的第一侧的第一侧栅叠层和形成在沟道区域的第二侧的第二侧栅叠层 与通道区域的第一侧相对。 在SONOS存储器件中，可以在每个SONOS存储器件中存储至少两位数据，从而允许半导体存储器件的集成密度增加而不增加其面积。

公开(公告)号：US20060108629A1

公开(公告)日：2006-05-25

申请号：US11220619

申请日：2005-09-08

申请人： Soo-doo Chae ,  Moon-kyung Kim ,  Jo-won Lee ,  Chung-woo Kim

发明人： Soo-doo Chae ,  Moon-kyung Kim ,  Jo-won Lee ,  Chung-woo Kim

IPC分类号： H01L29/788

CPC分类号： G11C16/0475 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/7923

摘要： A multi-bit non-volatile memory device and methods of operating and fabricating the same may be provided. The memory device may include a channel region formed in a semiconductor substrate, and a source and drain that form a Schottky contact with the channel region. Also, a central gate electrode may be located on a portion of the channel region, and first and second sidewall gate electrodes may be formed on the channel region along the outer sides of the central gate electrode. First and second storage nodes may be formed between the channel region and the sidewall gate electrodes.

摘要翻译： 可以提供多位非易失性存储器件及其操作和制造方法。 存储器件可以包括形成在半导体衬底中的沟道区，以及与沟道区形成肖特基接触的源极和漏极。 此外，中心栅电极可以位于沟道区的一部分上，并且第一和第二侧壁栅极可以沿着中心栅电极的外侧形成在沟道区上。 第一和第二存储节点可以形成在沟道区和侧壁栅电极之间。

公开(公告)号：US20060077743A1

公开(公告)日：2006-04-13

申请号：US11245426

申请日：2005-10-07

申请人： Sang-hun Jeon ,  Chung-woo Kim ,  Hyun-sang Hwang

发明人： Sang-hun Jeon ,  Chung-woo Kim ,  Hyun-sang Hwang

IPC分类号： G11C7/00

CPC分类号： H01L21/28273 ,  H01L29/513 ,  H01L29/7881

摘要： Memory devices and methods of manufacturing the same are provided. Memory devices may include a substrate, a source region and a drain region and a gate structure. The gate structure may be in contact with the source and drain regions, and may include a barrier layer. The barrier layer may be formed of at least two layers. The at least two layers may have different bandgap energies.

摘要翻译： 提供了存储器件及其制造方法。 存储器件可以包括衬底，源极区域和漏极区域以及栅极结构。 栅极结构可以与源极和漏极区域接触，并且可以包括阻挡层。 阻挡层可以由至少两层形成。 至少两层可能具有不同的带隙能量。

公开(公告)号：US20050205920A1

公开(公告)日：2005-09-22

申请号：US11070090

申请日：2005-03-03

申请人： Sang-hun Jeon ,  Chung-woo Kim ,  Dong-joon Ma ,  Sung-kyu Choi

发明人： Sang-hun Jeon ,  Chung-woo Kim ,  Dong-joon Ma ,  Sung-kyu Choi

IPC分类号： H01L21/8247 ,  H01L21/02 ,  H01L21/28 ,  H01L21/316 ,  H01L27/10 ,  H01L27/108 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L31/119

CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/28282 ,  H01L21/31616 ,  H01L21/31645 ,  H01L28/56 ,  H01L29/513 ,  H01L29/792

摘要： A SONOS type memory includes a semiconductor substrate, first and second impurity regions in the semiconductor substrate doped with impurity ions of a predetermined conductivity, separated a predetermined distance from each other, a channel region between the first and second impurity regions, and a data storage type stack on the semiconductor substrate between the first and second impurity regions. The data storage type stack includes a tunneling oxide layer, a memory node layer for storing data, a blocking oxide layer, and an electrode layer, which are sequentially formed. A dielectric constant of the memory node layer is higher than dielectric constants of the tunneling and the blocking oxide layers, and a band offset of the memory node layer is lower than band offsets of the tunneling and the blocking oxide layers. The tunneling oxide layer and the blocking oxide layer are high dielectric insulating layers.

摘要翻译： SONOS型存储器包括半导体衬底，掺杂有预定电导率的杂质离子的半导体衬底中的第一和第二杂质区，彼此隔开预定距离，第一和第二杂质区之间的沟道区，以及数据存储 在第一和第二杂质区之间的半导体衬底上。 数据存储型堆叠包括依次形成的隧道氧化物层，用于存储数据的存储节点层，阻挡氧化物层和电极层。 存储节点层的介电常数高于隧道和阻塞氧化物层的介电常数，并且存储器节点层的带偏移低于隧道和阻塞氧化物层的带偏移。 隧道氧化物层和阻挡氧化物层是高介电绝缘层。