公开(公告)号：US06960514B2

公开(公告)日：2005-11-01

申请号：US10803395

申请日：2004-03-18

申请人： Jochen Beintner ,  Rama Divakaruni ,  Johnathan Faltermeier ,  Philip L. Flaitz ,  Oleg Gluschenkov ,  Carol J. Heenan ,  Rajarao Jammy ,  Byeong Kim ,  Mihel Seitz ,  Akira Sudo ,  Yoichi Takegawa

发明人： Jochen Beintner ,  Rama Divakaruni ,  Johnathan Faltermeier ,  Philip L. Flaitz ,  Oleg Gluschenkov ,  Carol J. Heenan ,  Rajarao Jammy ,  Byeong Kim ,  Mihel Seitz ,  Akira Sudo ,  Yoichi Takegawa

IPC分类号： H01L21/762

CPC分类号： H01L21/76224

摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

摘要翻译： 对于给定的栅极长度，对于晶体管导通电流的增加，晶体管串联电阻的降低和接触电阻的降低，用于场效应晶体管的改进的投池形有源区域。 投球形有源区结构包括形成在衬底中的至少两个浅沟槽绝缘体（STI）结构，其限定有源区域结构，其包括宽度比底部宽的加宽顶部部分。 还描述了一种用于形成改进的捕鱼器活性区域的改进的制造方法，其实现了形成STI结构图形的步骤，随后是将基板材料迁移到图案的至少部分中的步骤，从而形成活动的加宽顶部 区域结构。 本发明的制造方法在不使用光刻的情况下形成投手型有源区域，因此不受光刻工具的最小基准规则的限制。

公开(公告)号：US20050151181A1

公开(公告)日：2005-07-14

申请号：US10707754

申请日：2004-01-09

申请人： Jochen Beintner ,  Rama Divakaruni ,  Rajarao Jammy

发明人： Jochen Beintner ,  Rama Divakaruni ,  Rajarao Jammy

IPC分类号： H01L21/8242 ,  H01L21/762 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10894

摘要： A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate conductor and a boron-doped channel. The method includes forming trenches adjacent the DRAM cell and a silicon-oxy-nitride isolation liner on either side of the DRAM cell, adjacent the gate conductor. Isolation regions are then formed in the trenches on either side of the DRAM cell. Thereafter, the DRAM cell, including the boron-containing channel region adjacent the gate conductor, is subjected to elevated temperatures by thermal processing, for example, forming a support device on the substrate adjacent the isolation regions. The nitride-containing isolation liner reduces segregation of the boron in the channel region, as compared to an essentially nitrogen-free oxide-containing isolation liner.

摘要翻译： 一种制造集成电路器件的方法包括蚀刻衬底中的沟槽并形成具有位于下端的存储电容器的动态随机存取存储器（DRAM）单元和覆盖的垂直金属氧化物半导体场效应晶体管（MOSFET），其包括栅极 导体和掺硼通道。 该方法包括在DRAM单元附近形成沟槽和在DRAM单元的任一侧上与栅极导体相邻的硅 - 氮氧化物隔离衬垫。 然后在DRAM单元的两侧的沟槽中形成隔离区。 此后，包括与栅极导体相邻的含硼沟道区域的DRAM单元通过热处理受到升高的温度，例如，在邻近隔离区域的衬底上形成支撑器件。 与基本上不含氮氧化物的隔离衬垫相比，含氮化物的隔离衬垫减少了沟道区域中的硼的偏析。

公开(公告)号：US20050124101A1

公开(公告)日：2005-06-09

申请号：US10730582

申请日：2003-12-08

申请人： Jochen Beintner

发明人： Jochen Beintner

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L29/785 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66628 ,  H01L29/66818

摘要： In a FinFET integrated circuit, the fins are formed with a body thickness in the body area and then thickened in the source/drain area outside the body to improve conductivity. The thickening is performed with epitaxial deposition while the gates are covered by a composite gate cover layer to prevent thickening of the gates, which may short the gate to the source/drain.

摘要翻译： 在FinFET集成电路中，翅片在体区域中形成为具有体厚度，然后在身体外部的源极/漏极区域中增厚以提高导电性。 通过外延沉积进行增厚，而栅极被复合栅极覆盖层覆盖以防止栅极增厚，这可能使源极/漏极的栅极短路。

公开(公告)号：US06790739B2

公开(公告)日：2004-09-14

申请号：US10249997

申请日：2003-05-27

申请人： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

发明人： Rajeev Malik ,  Larry Nesbit ,  Jochen Beintner ,  Rama Divakaruni

IPC分类号： H01L2120

CPC分类号： H01L27/10894 ,  H01L21/76224 ,  H01L27/10861

摘要： A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.

摘要翻译： 公开了一种用于处理半导体存储器件的方法，所述存储器件包括阵列区域和其上的支撑区域。 在本发明的示例性实施例中，该方法包括从阵列区域去除在器件上形成的初始衬垫氮化物材料。 然而，支撑区域中的初始衬垫氮化物材料仍然保持。 然后在阵列区域内形成有源器件区域，其中保持在支撑区域中的初始衬垫氮化物有助于保护支撑区域免受在阵列区域内形成有源器件区域期间实现的湿蚀刻工艺。

公开(公告)号：US06770526B2

公开(公告)日：2004-08-03

申请号：US10294100

申请日：2002-11-14

申请人： Michael P. Chudzik ,  Jochen Beintner ,  Joseph F. Shepard, Jr.

发明人： Michael P. Chudzik ,  Jochen Beintner ,  Joseph F. Shepard, Jr.

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L27/10817 ,  H01L29/66181 ,  H01L29/945

摘要： A semiconductor device is fabricated using a micro-masking structure. The micro-masking structure is formed along the sidewalls of a trench in a semiconductor substrate or along the sidewalls of an electrode disposed over the semiconductor substrate. The micro-masking structure exposes portions of the sidewalls and covers other portions of the sidewalls. Then the exposed portions of the sidewalls are recessed to form a plurality of recesses such that the sidewalls have an increase surface area. After the recessing, the micro-masking structure is removed. The recessed sidewalls provide enhanced capacitance.

公开(公告)号：US06677205B2

公开(公告)日：2004-01-13

申请号：US09966644

申请日：2001-09-28

申请人： Jochen Beintner

发明人： Jochen Beintner

IPC分类号： H01L21336

CPC分类号： H01L27/10876 ,  H01L21/823487 ,  H01L27/10864 ,  H01L27/10888 ,  H01L27/10891

摘要： Alignment tolerance for a vertical gate transistor device can be relaxed because of a spacer formed adjacent the trench. The gate electrode is formed of two materials that have etch selectivity between them, such that the outer material can be etched a predetermined depth into the recess without etching the inner material, resulting in the formation of a divot at the top of the trench. The divot is filled with an insulating material so that if source drain contacts are misaligned, the spacer serves to insulate the gate electrode from the contacts.

摘要翻译： 由于在沟槽附近形成间隔物，因此垂直栅极晶体管器件的对准公差可以被放宽。 栅电极由两种在其间具有蚀刻选择性的材料形成，使得外部材料可以在没有蚀刻内部材料的情况下蚀刻到凹部中的预定深度，导致在沟槽顶部形成凹陷。 该凹陷填充有绝缘材料，使得如果源极漏极接触不对准，则间隔件用于使栅电极与触点绝缘。

公开(公告)号：US06667504B1

公开(公告)日：2003-12-23

申请号：US10249228

申请日：2003-03-24

申请人： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

发明人： Jochen Beintner ,  Wolfgang Bergner ,  Richard A. Conti ,  Andreas Knorr ,  Rolf Weis

IPC分类号： H01L27108

CPC分类号： H01L27/10867 ,  H01L27/10864 ,  H01L29/945

摘要： The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.

摘要翻译： 本发明提供了一种沟槽存储结构，其包括具有沟槽的衬底，沟槽下部的电容器导体，与电容器导体相邻的沟槽中的导电节点带，电容器导体上方的沟槽顶部氧化物，以及导电 埋在衬底中的邻近沟槽顶部氧化物的衬底。 沟槽顶部氧化物包括导电带上方的掺杂沟槽顶部氧化物层和掺杂沟槽顶部氧化物层上方的未掺杂沟槽顶部氧化物层。

公开(公告)号：US06602745B2

公开(公告)日：2003-08-05

申请号：US10066206

申请日：2002-01-31

申请人： Peter Thwaite ,  Jochen Beintner

发明人： Peter Thwaite ,  Jochen Beintner

IPC分类号： H01L21338

CPC分类号： H01L29/1033 ,  H01L21/76235

摘要： An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge of the channel region. A method of controlling the shape of the edge of the channel region is to limit the supply of oxygen to the region at the edge of the channel region during the oxidation process when the side walls of the silicon island, in which the transistor will be formed, are initially covered with a layer of silicon oxide.

公开(公告)号：US06348394B1

公开(公告)日：2002-02-19

申请号：US09573375

申请日：2000-05-18

申请人： Jack A. Mandelman ,  Rama Divakaruni ,  Herbert Ho ,  Giuseppe La Rosa ,  Yujun Li ,  Jochen Beintner ,  Radhika Srinivasan

发明人： Jack A. Mandelman ,  Rama Divakaruni ,  Herbert Ho ,  Giuseppe La Rosa ,  Yujun Li ,  Jochen Beintner ,  Radhika Srinivasan

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L21/76224

摘要： A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.

摘要翻译： 提供半导体器件及其制造方法。 在半导体衬底中形成沟槽。 优选在沟槽的表面上形成薄的氧化物衬垫。 氮化物衬垫形成在沟槽中。 电荷被困在氮化物衬垫中。 在优选实施例中，沟槽通过HDP工艺填充氧化物以增加在氮化物衬垫中捕获的电荷量。 优选地，氧化物填充物直接形成在氮化物衬垫上。

公开(公告)号：US06329271B1

公开(公告)日：2001-12-11

申请号：US09588244

申请日：2000-06-06

申请人： Hiroyuki Akatsu ,  Yujun Li ,  Jochen Beintner

发明人： Hiroyuki Akatsu ,  Yujun Li ,  Jochen Beintner

IPC分类号： H01L21425

CPC分类号： H01L29/66583 ,  H01L21/823412 ,  H01L29/105

摘要： A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity concentration. The buried layer is below the channel region and essentially extends only the distance between the drain and source regions of the transistor. The process to form the device provides high concentration in the region under the gate to suppress lateral depletion region expansion, while keeping a gradual junction in the vertical direction.

摘要翻译： 短沟道绝缘栅场效应晶体管在半导体本体内部具有与晶体管相同的导电类型的掩埋层，但具有较高的杂质浓度。 掩埋层在沟道区下方，并且基本上只延伸晶体管的漏极和源极区之间的距离。 形成器件的过程在栅极下方的区域提供高浓度，以抑制横向耗尽区域膨胀，同时保持垂直方向上的逐渐连接。