公开(公告)号：US5386045A

公开(公告)日：1995-01-31

申请号：US924952

申请日：1992-08-05

Applicant: Upali Weerasooriya ,  Donald T. Robertson ,  John Lin ,  Bruce E. Leach ,  Cynthia L. Aeschbacher ,  Tonyette S. Sandoval

Inventor： Upali Weerasooriya ,  Donald T. Robertson ,  John Lin ,  Bruce E. Leach ,  Cynthia L. Aeschbacher ,  Tonyette S. Sandoval

IPC: C07C67/26 ,  C07C69/96

CPC classification number: C07C67/26

Abstract: A process for producing alkoxylated mono-, di-, and tri-esters in which a starting material ester and an alkylene oxide are reacted in the presence of selected calcium based catalysts.

Abstract translation: 一种制备烷氧基化单 - ，二 - 和三 - 酯的方法，其中原料酯和烯化氧在选择的钙基催化剂存在下反应。

公开(公告)号：US5356822A

公开(公告)日：1994-10-18

申请号：US184516

申请日：1994-01-21

Applicant: John Lin ,  Andras F. Cserhati

Inventor： John Lin ,  Andras F. Cserhati

IPC: H01L21/8249 ,  H01L27/12 ,  H01L21/265

CPC classification number: H01L27/1203 ,  H01L21/8249 ,  Y10S148/009

Abstract: A method for making all complementary BiCDMOS devices on a SOI substrate (10). Isolated n.sup.- and p.sup.- regions (20,32,34,36,40,42) are formed on the silicon layer (16) and oxidized. LOCOS oxide regions (28) are formed on selected pairs of the n.sup.- and p.sup.- regions on which gates (44) for complementary DMOS device (114,116) and field plates (46) for complementary bipolar devices (118,120) are formed. Gates (48) for complementary MOS devices (122,124) are formed directly on the oxidized silicon layer (24). N-type and p-type dopants are then implanted into the silicon layer (16) forming n body and p body areas (54,56,58,60). Selected n.sup.+ and p.sup.+ areas (66,68) are formed in the n body and p body areas (54,56,58,60) as well as selected areas of n.sup.- and p.sup.- regions (30,32,34,36,40,42). The substrate (10) is then covered with an oxide layer and windows etched therethrough to expose said n.sup.+ and p.sup.+ areas (66,68) and selected areas of the gates (44,48) and field plates (46). Metal electrical contacts (78-112) are deposited through the windows to the n.sup.+ and p.sup.+ areas ( 66,68) and the gates (44,48) and field plates (46).

Abstract translation: 一种在SOI衬底（10）上制造所有互补BiCDMOS器件的方法。 隔离的n-和p-区（20,32,34,36,40,42）形成在硅层（16）上并被氧化。 LOCOS氧化物区域（28）形成在其上形成用于互补DMOS器件（114,116）的栅极（44）和用于互补双极器件（118,120）的场板（46）的n区和p-区的选定对上。 用于互补MOS器件（122,124）的栅极（48）直接形成在氧化硅层（24）上。 然后将N型和p型掺杂剂注入形成n体和p体区（54,56,58,60）的硅层（16）中。 选择的n +和p +区域（66,68）形成在n体和p体区域（54,56,58,60）以及n区和p-区的选定区域（30,32,34,36， 40,42）。 然后用氧化物层覆盖衬底（10），并且通过其蚀刻窗口以暴露出栅极（44,48）和场板（46）的所述n +和p +区域（66,68）和选定区域。 金属电触点（78-112）通过窗口沉积到n +和p +区域（66,68）和栅极（44,48）和场板（46）上。

公开(公告)号：US20160255873A1

公开(公告)日：2016-09-08

申请号：US15152400

申请日：2016-05-11

Applicant: Yang Tao ,  John Lin ,  Xin Chen ,  Gary E. Seibel

Inventor： Yang Tao ,  John Lin ,  Xin Chen ,  Gary E. Seibel

IPC: A23N15/02 ,  B26D7/06 ,  B26F3/00 ,  B26D5/00

CPC classification number: A23N15/02 ,  A23L19/03 ,  B26D5/00 ,  B26D5/007 ,  B26D5/34 ,  B26D7/0625 ,  B26F3/004

Abstract: A system and methods are provided for removal of undesired portions of a fruit or vegetable, such as removal of calyxes from strawberries before they are flash frozen. An automated process for high-throughput fruit or vegetable calyx removal includes a loading system, an identification system, and a removal system. The loading system is configured to transport the fruit or vegetable through the automated process. The loading system may also orient the fruits or vegetables along an axis of the fruit and or align the fruit or vegetables in a desired pattern, orientation, and/or arrangement. The identification system is configured to locate the calyx and determines calyx position data and an optimal cutting path for individual fruit. The removal system uses data received from the identification system to separate the calyx from the fruit or vegetable.

Abstract translation: 提供了用于去除水果或蔬菜的不期望的部分的系统和方法，例如在快速冷冻之前从草莓中除去花萼。 用于高通量水果或蔬菜花萼去除的自动化过程包括加载系统，识别系统和去除系统。 装载系统配置为通过自动化过程运输水果或蔬菜。 装载系统还可以沿水果的轴线定向水果或蔬菜，或者以所需的图案，取向和/或布置方式对准水果或蔬菜。 识别系统被配置为定位花萼并且确定花萼位置数据和用于单个果实的最佳切割路径。 去除系统使用从识别系统接收的数据将花萼与水果或蔬菜分开。

公开(公告)号：US08878330B2

公开(公告)日：2014-11-04

申请号：US13567456

申请日：2012-08-06

Applicant: Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

Inventor： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

IPC: H01L29/02 ,  H01L21/761 ,  H01L21/266

CPC classification number: H01L21/761 ,  H01L21/266

Abstract: An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.

Abstract translation: 一种集成电路，包括分压器，该分压器具有围绕中心开口的场氧化物上的非硅栅极材料的上电阻器，以及位于上电阻器下的漂移层的输入端子，所述输入端子与所述上电阻器的输入节点相邻， 场氧化物并通过中心开口耦合到漂移层，感测端子耦合到与输入节点相反的上电阻上的感测节点，具有耦合到感测端子的检测节点和参考节点的下电阻器，以及 参考终端耦合到参考节点。 形成包含分压器的集成电路的工艺。

公开(公告)号：US08274131B2

公开(公告)日：2012-09-25

申请号：US12962159

申请日：2010-12-07

Applicant: Sameer P. Pendharkar ,  John Lin ,  Philip L. Hower ,  Steven L. Merchant

Inventor： Sameer P. Pendharkar ,  John Lin ,  Philip L. Hower ,  Steven L. Merchant

IPC: H01L21/70

CPC classification number: H01L21/8249 ,  H01L21/76232 ,  H01L27/0623

Abstract: A semiconductor device comprising a first transistor device (130) on or in a semiconductor substrate (115) and a second transistor device (132) on or in the substrate. The device further comprises an insulating trench (200) located between the first transistor device and the second transistor device. At least one upper corner (610) of the insulating trench is a rounded corner in a lateral plane (620) of the substrate.

Abstract translation: 一种半导体器件，包括在半导体衬底（115）上或半导体衬底（115）中的第一晶体管器件（130）和衬底上或衬底中的第二晶体管器件（132）。 该器件还包括位于第一晶体管器件和第二晶体管器件之间的绝缘沟槽（200）。 绝缘沟槽的至少一个上角（610）是衬底的横向平面（620）中的圆角。

公开(公告)号：US20120098062A1

公开(公告)日：2012-04-26

申请号：US13281260

申请日：2011-10-25

Applicant: Sameer P. Pendharkar ,  John Lin

Inventor： Sameer P. Pendharkar ,  John Lin

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L29/66681 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0882 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/7816

Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.

Abstract translation: 集成电路包括具有并行交替有源间隙漂移区和场间隙漂移区的扩展漏极MOS晶体管。 扩展漏极MOS晶体管包括在场间隙漂移区域上具有场板的栅极。 扩展漏极MOS晶体管可以形成为对称嵌套配置。 用于形成包含延伸漏极MOS晶体管的集成电路的工艺提供并行的交替有源间隙漂移区域和场间隙漂移区域，栅极在场间隙漂移区域上具有场板。

公开(公告)号：US20110275210A1

公开(公告)日：2011-11-10

申请号：US13188162

申请日：2011-07-21

Applicant: Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

Inventor： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

IPC: H01L21/28

CPC classification number: H01L29/7813 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66734

Abstract: An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.

Abstract translation: 电子器件具有形成在半导体层中的多个沟槽。 垂直漂移区域位于沟槽之间和相邻的沟槽之间。 电极位于每个沟槽内，电极具有栅电极部分和场板部分。 在场板部分和垂直漂移区域之间设置具有较大深度的厚度增加的分级场板电介质。

公开(公告)号：USRE42498E1

公开(公告)日：2011-06-28

申请号：US11256619

申请日：2005-10-21

Applicant: Ming-Chung Tang ,  John Lin

Inventor： Ming-Chung Tang ,  John Lin

IPC: H04N1/04

CPC classification number: H04N1/00681 ,  H04N1/00702 ,  H04N1/0071 ,  H04N1/00713 ,  H04N1/00734 ,  H04N1/0074 ,  H04N1/00748 ,  H04N1/00755 ,  H04N1/00774 ,  H04N1/0402 ,  H04N1/0405 ,  H04N1/0443 ,  H04N1/0455 ,  H04N1/121 ,  H04N1/128 ,  H04N1/1911 ,  H04N2201/04755 ,  H04N2201/04789

Abstract: A wide image scanner which can scan the image of a large scale original using only a regular image sensor is provided. The invention includes a sliding shaft, an image reading device, a number of paper width sensors, a paper edge sensor, and a control module. Whenever the paper edge sensor detects the presence of an end edge of the original, it will send a vertical control signal to the control module to control the rotation direction of the rollers. On the other hand, the paper width sensors detect the width of the original and send the horizontal control signals to the control module. From the horizontal control signals, the control module can determine the number of horizontal displacement positions and control the horizontal displacement each time for the image reading device after the paper edge sensor detects the end edge of the original. The procedure continues until the image reading device has been moved to the final displacement position predetermined by the horizontal control signal. Consequently, the entire image of the origin can automatically be read portion by portion without manual operation.

Abstract translation: 提供了可以仅使用常规图像传感器来扫描大尺寸原稿的图像的宽幅图像扫描仪。 本发明包括滑动轴，图像读取装置，多个纸张宽度传感器，纸张边缘传感器和控制模块。 每当纸张边缘传感器检测到原稿的端部边缘时，它将向控制模块发送垂直控制信号，以控制滚轮的旋转方向。 另一方面，纸张宽度传感器检测原稿的宽度，并将水平控制信号发送到控制模块。 从水平控制信号，控制模块可以确定水平位移位置的数量，并且在纸张边缘传感器检测到原稿的端边缘之后，每次对图像读取装置控制水平位移。 该过程继续，直到图像读取装置已经移动到由水平控制信号预定的最终位移位置。 因此，原点的整个图像可以自动地逐个读取，而无需手动操作。

公开(公告)号：US07953057B2

公开(公告)日：2011-05-31

申请号：US12704439

申请日：2010-02-11

Applicant: Sherman Lee ,  Vivian Chou ,  Charles Aragones ,  John Lin

Inventor： Sherman Lee ,  Vivian Chou ,  Charles Aragones ,  John Lin

IPC: H04W40/00

CPC classification number: H04W88/06 ,  H04W28/14 ,  H04W84/12

Abstract: A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective. The processor operates to maintain the audio pattern when additional packetized audio data is received by the WLAN interface. These operations are also performed for the output buffer, which receives packetized audio data from the transcoder and writes the packetized audio data to the WLAN interface.

Abstract translation: 无线局域网（WLAN）收发集成电路包括WLAN接口，输入缓冲器，输入缓冲器控制器和处理器。 WLAN收发集成电路还可以包括输出缓冲器，输出缓冲器控制器，代码转换器和/或音频编解码器（CODEC）。 WLAN收发集成电路安装在服务语音通信的WLAN设备中。 输入缓冲区从WLAN接口接收分组化音频数据。 当输入缓冲器满足缓冲空缺阈值时，处理器和输入缓冲器控制器协同工作，以便用分组化音频数据填充输入缓冲器的至少一部分。 处理器从输入缓冲器复制分组化的音频数据，并用复制的分组化音频数据填充输入缓冲器，以保持输入缓冲器中的音频模式。 当处理器可用并且复制/填充不再有效之后，输入缓冲器控制器填充输入缓冲器。 当附加的分组化音频数据被WLAN接口接收时，处理器操作以维持音频模式。 这些操作也对输出缓冲器执行，输出缓冲器从代码转换器接收打包的音频数据，并将打包的音频数据写入WLAN接口。

公开(公告)号：US07846789B2

公开(公告)日：2010-12-07

申请号：US11873205

申请日：2007-10-16

Applicant: Sameer P. Pendharkar ,  John Lin ,  Philip L. Hower ,  Steven L. Merchant

Inventor： Sameer P. Pendharkar ,  John Lin ,  Philip L. Hower ,  Steven L. Merchant

IPC: H01L21/8238

CPC classification number: H01L21/8249 ,  H01L21/76232 ,  H01L27/0623

Abstract: A semiconductor device comprising a first transistor device on or in a semiconductor substrate and a second transistor device on or in the substrate. The device further comprises an insulating trench located between the first transistor device and the second transistor device. At least one upper corner of the insulating trench is a rounded corner in a lateral plane of the substrate.

Abstract translation: 一种半导体器件，包括半导体衬底上或半导体衬底中的第一晶体管器件和衬底上或衬底中的第二晶体管器件。 该器件还包括位于第一晶体管器件和第二晶体管器件之间的绝缘沟槽。 绝缘沟槽的至少一个上角是衬底的横向平面中的圆角。