公开(公告)号：US20100308400A1

公开(公告)日：2010-12-09

申请号：US12431852

申请日：2009-04-29

申请人： Mohamed N. Darwish ,  Jun Zeng

发明人： Mohamed N. Darwish ,  Jun Zeng

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734

摘要： A method of fabricating a trench device includes forming a first trench and forming a hardmask layer on sidewalls of the trench. A second trench may be etched narrower than the first trench, into the bottom of the first trench. A dielectric material may be grown to substantially fill the second trench, using a reaction process to which the hardmask material is substantially inert. The growing action also grows tapered portions of the dielectric material upwardly under part of the hardmask. A conductive layer may be formed over said dielectric material. The dielectric material in the second trench, in combination with the tapered portions which extend upward from the dielectric material may provide smooth gradation of voltage differences within the semiconductor material. The gradation may be caused by potential differences between the gate and various portions of the semiconductor material.

摘要翻译： 制造沟槽器件的方法包括形成第一沟槽并在沟槽的侧壁上形成硬掩模层。 可以将第二沟槽蚀刻成比第一沟槽更窄，进入第一沟槽的底部。 可以使用硬掩模材料基本上是惰性的反应过程来生长电介质材料以基本上填充第二沟槽。 增长的作用还使硬介面的一部分向上延伸介电材料的锥形部分。 可以在所述电介质材料上形成导电层。 第二沟槽中的电介质材料与从电介质材料向上延伸的锥形部分组合可提供半导体材料内的电压差的平滑等级。 灰度可能由栅极与半导体材料的各个部分之间的电位差引起。

公开(公告)号：US07799642B2

公开(公告)日：2010-09-21

申请号：US11866365

申请日：2007-10-02

申请人： Shih Tzung Su ,  Jun Zeng ,  Poi Sun ,  Kao Way Tu ,  Tai Chiang Chen ,  Long Lv ,  Xin Wang

发明人： Shih Tzung Su ,  Jun Zeng ,  Poi Sun ,  Kao Way Tu ,  Tai Chiang Chen ,  Long Lv ,  Xin Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A method for manufacturing a trench MOSFET semiconductor device comprises: providing a heavily doped N+ silicon substrate; forming an N type epitaxial layer; forming a thick SiO2 layer; creating P body and source area formations by ion implantation without any masks; utilizing a first mask to define openings for a trench gate and a termination; thermally growing a gate oxide layer followed by formation of a thick poly-Silicon refill layer without a mask to define a gate bus area; forming sidewall spacers; forming P+ areas; removing the sidewall spacers; depositing tungsten to fill contacts and vias; depositing a first thin barrier metal layer; depositing a first thick metal layer; utilizing a second metal mask to open a gate bus area; forming second sidewall spacers; depositing a second thin barrier metal layer; depositing a second thick metal layer; and planarizing at least the second thick metal layer and the second thin metal layer to isolate the source metal portions from gate metal portions, whereby the trench MOSFET semiconductor device is manufactured utilizing only first and second masks.

摘要翻译： 一种用于制造沟槽MOSFET半导体器件的方法包括：提供重掺杂的N +硅衬底; 形成N型外延层; 形成厚的SiO 2层; 通过离子注入创建P体和源区形成，而不需要任何掩模; 利用第一掩模来限定沟槽栅极和终端的开口; 热生长栅极氧化层，随后形成厚度不含掩模的多晶硅替代层，以限定栅极总线面积; 形成侧壁间隔物; 形成P +区域; 去除侧壁间隔物; 沉积钨以填充触点和通孔; 沉积第一薄的阻挡金属层; 沉积第一厚金属层; 利用第二金属掩模打开闸总线区域; 形成第二侧壁间隔物; 沉积第二薄的阻挡金属层; 沉积第二厚金属层; 并且至少平面化第二厚金属层和第二薄金属层以将源极金属部分与栅极金属部分隔离，由此仅利用第一和第二掩模制造沟槽MOSFET半导体器件。

公开(公告)号：US07166866B2

公开(公告)日：2007-01-23

申请号：US10882387

申请日：2004-07-02

申请人： Jun Zeng ,  Gary Mark Dolry ,  Praveen MurAleedharan

发明人： Jun Zeng ,  Gary Mark Dolry ,  Praveen MurAleedharan

IPC分类号： H01L29/15

CPC分类号： H01L29/0615 ,  H01L29/1608 ,  H01L29/267 ,  Y10S438/931

摘要： A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer. A well region of a second, opposite conduction type is formed at the upper surface of the upper layer adjacent the edge termination zone, and an oxide layer is formed over the upper layer and edge termination zone.

摘要翻译： 硅半导体管芯包括重掺杂硅衬底以及设置在衬底上的包含第一导电类型的掺杂硅的上层。 上层包括邻近边缘终止区的第二相反导电类型的阱区，其包括具有比硅更高的临界电场的材料层。 阱区域和相邻边缘终止区域都设置在上层的上表面，并且氧化物层覆盖在上层和边缘终止区域上。 一种用于形成具有改进的边缘终止的硅模的方法。 该方法包括在重掺杂的硅衬底上形成包括第一导电类型的掺杂硅的上层，并形成边缘终止区，该边缘终止区包括在上层的上表面处具有比硅更高的临界电场的材料层 层。 第二相反导电类型的阱区形成在邻近边缘终止区的上层的上表面处，并且在上层和边缘终止区上形成氧化物层。

公开(公告)号：US20060255374A1

公开(公告)日：2006-11-16

申请号：US11194354

申请日：2005-08-01

申请人： Jun Zeng ,  Po-I Sun

发明人： Jun Zeng ,  Po-I Sun

IPC分类号： H01L29/80

CPC分类号： H01L29/42316 ,  H01L23/482 ,  H01L29/0619 ,  H01L29/1066 ,  H01L29/66901 ,  H01L29/8083 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing process and a power junction field-effect transistor (JFET) are provided. The basic concept of the present invention is to allow the current to flow vertically from the drain region on the bottom side to the source region on the topside of the device. By regulating the voltage applied between the gate regions and the source region, the power junction field-effect transistor (JFET) of the present invention can be built to handle large current and higher voltage for power management purposes, as is similar to the metal oxide semiconductor field effect transistor (MOSFET).

摘要翻译： 提供制造工艺和功率结场效应晶体管（JFET）。 本发明的基本概念是允许电流从底侧的漏极区域到器件的顶侧上的源极区域垂直流动。 通过调节施加在栅极区域和源极区域之间的电压，可以构建本发明的功率结场效应晶体管（JFET），以处理用于电力管理目的的大电流和较高电压，类似于金属氧化物 半导体场效应晶体管（MOSFET）。

公开(公告)号：US07105228B2

公开(公告)日：2006-09-12

申请号：US10113292

申请日：2002-04-02

申请人： Johannes Averdung ,  Andreas Greiner ,  Joachim H. Wendorff ,  Haoquing Hou ,  Michael Bognitzki ,  Jun Zeng

发明人： Johannes Averdung ,  Andreas Greiner ,  Joachim H. Wendorff ,  Haoquing Hou ,  Michael Bognitzki ,  Jun Zeng

IPC分类号： B05B5/00 ,  B82B3/00 ,  D01D5/24

CPC分类号： D01D5/003 ,  B01D67/003 ,  B01D67/0037 ,  B01D69/08 ,  B01D69/12 ,  B01D71/022 ,  B01D71/72 ,  B01D2323/24 ,  B01D2323/39 ,  B01D2325/10 ,  B01J35/06 ,  D01D5/24 ,  D01F8/10 ,  D01F8/18 ,  D06M15/37 ,  Y10T428/131 ,  Y10T428/2913 ,  Y10T428/2935 ,  Y10T428/2973 ,  Y10T428/2975

摘要： The present invention relates to a method for making shaped structures with internally coated cavities with an inside diameter in the nanometer to micrometer range and the shaped structure obtained thereby.

摘要翻译： 本发明涉及一种用于制造内径为内径为纳米至微米范围的内部涂覆空腔的成形结构的方法，以及由此获得的成形结构。

公开(公告)号：US20060006460A1

公开(公告)日：2006-01-12

申请号：US11178215

申请日：2005-07-08

申请人： Jun Zeng

发明人： Jun Zeng

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/749

摘要： The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

公开(公告)号：US20050224868A1

公开(公告)日：2005-10-13

申请号：US11091733

申请日：2005-03-28

申请人： Christopher Kocon ,  Jun Zeng

发明人： Christopher Kocon ,  Jun Zeng

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397

摘要： An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions. A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer. A process for forming an improved MOS-gate device provides a device whose gate trench is filled to a selected level with a conductive gate material, over which is formed an isolation dielectric layer whose upper surface is substantially coplanar with the upper surface of the upper layer of the device.

摘要翻译： 改进的沟槽MOS门控器件包括单晶半导体衬底，其上配置有掺杂的上层。 上层在上表面包括具有第一极性的多个重掺杂体区域，并且覆盖在漏极区域上。 上层还在其上表面包括具有与身体区域相反的第二极性的多个重掺杂源区。 栅极沟槽从上层的上表面延伸到漏极区，并且将一个源极区域与另一个源区域分离。 沟槽具有包括介电材料层的底板和侧壁，并且包含填充到选定电平的导电栅极材料和覆盖栅极材料并基本上填充沟槽的介电材料隔离层。 因此，沟槽中的上层电介质材料的上表面与上层的上表面基本上共面。 用于形成改进的MOS栅极器件的工艺提供了一种器件，其栅极沟槽被填充到具有导电栅极材料的选定的电平，在其上形成隔离电介质层，其上表面与上层的上表面基本共面 的设备。

公开(公告)号：US06242784B1

公开(公告)日：2001-06-05

申请号：US09344868

申请日：1999-06-28

申请人： Jun Zeng ,  Gary Mark Dolry ,  Praveen MurAleedharan

发明人： Jun Zeng ,  Gary Mark Dolry ,  Praveen MurAleedharan

IPC分类号： H01L2976

CPC分类号： H01L29/0615 ,  H01L29/1608 ,  H01L29/267 ,  Y10S438/931

摘要： A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer. A well region of a second, opposite conduction type is formed at the upper surface of the upper layer adjacent the edge termination zone, and an oxide layer is formed over the upper layer and edge termination zone.

公开(公告)号：US06218701B1

公开(公告)日：2001-04-17

申请号：US09303270

申请日：1999-04-30

申请人： Dexter Elson Semple ,  Jun Zeng

发明人： Dexter Elson Semple ,  Jun Zeng

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/0657 ,  H01L29/4232 ,  H01L29/4238

摘要： A power MOS device that has increased channel width comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a plurality of doped well regions of a second, opposite conduction type and a plurality of heavily doped source regions of the first conduction type at an etched upper surface of the upper layer that comprises parallel corrugations disposed transversely to the source regions. A gate that separates one source region from another comprises an insulating layer and a conductive material. The corrugations provide an increase in width of a channel underlying the gate and the well and source regions. In a process for forming a power MOS device with increased channel width on a semiconductor substrate having a doped upper layer of a first conduction type, a stripe mask is formed on an upper surface of the upper layer, and the upper surface is selectively etched to form a corrugated surface comprising a plurality of parallel corrugations. Following removal of the stripe mask, an insulating layer is formed on the corrugated surface, and an overlying conductive layer is formed on the insulating layer, the insulating and conductive layers comprising a corrugated gate region disposed transversely to the parallel corrugations of the upper surface. A dopant of a second, opposite conduction type is implanted to form a doped well region in the upper layer, and a dopant of the first conduction type is implanted into a portion of the corrugated surface adjacent to the gate, thereby forming a heavily doped source region in the upper layer. In an alternative procedure for forming a gate, a gate trench having a floor comprising parallel corrugations that substantially correspond to the corrugations in the upper surface is etched into the upper layer. Following lining of the trench floor and sidewalls with an insulating layer, the trench is substantially filled with a conductive material to form a gate trench. A dopant of the first conduction type is implanted into a portion of the corrugated surface adjacent to the gate region, thereby forming a heavily doped source region in the upper layer.

公开(公告)号：US08680607B2

公开(公告)日：2014-03-25

申请号：US13525908

申请日：2012-06-18

申请人： Jun Zeng ,  Mohamed N. Darwish

发明人： Jun Zeng ,  Mohamed N. Darwish

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

摘要： Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps.

摘要翻译： 功率器件和相关工艺，其中栅极和场板沟槽都具有多个阶梯宽度，采用自对准工艺步骤。