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    Semiconductor memory device having a small-sized memory chip and a decreased power-supply noise
    51.
    发明授权
    Semiconductor memory device having a small-sized memory chip and a decreased power-supply noise 失效
    具有小型存储芯片的半导体存储器件和电源噪声降低

    公开(公告)号：US06762968B2

    公开(公告)日：2004-07-13

    申请号：US10322405

    申请日：2002-12-17

    申请人： Yashiro Suematsu ,  Masaru Koyanagi

    发明人： Yashiro Suematsu ,  Masaru Koyanagi

    IPC分类号： G11C700

    CPC分类号： G11C7/12 ,  G11C11/4074 ,  G11C11/4094

    摘要： The bit line overdrive circuit of the present invention comprises a VBLH potential generation circuit generating a bit line final potential relative to a VBLH power supply line for driving a sense amplifier, a charge adjusting capacitance C, a transistor for supplying an overdrive potential to the VBLH power supply line, and a transistor for connecting a PCS node to the VBLH power supply line. The charge pre-charged from the overdrive potential to the VBLH power supply line is shared among the capacitance of the above-noted circuit elements connected to the VBLH power supply line, the bit line capacitance, and the capacitance of a cell capacitor so as to form a VBLH power supply of a substantially one system, thereby avoiding the generation of a power supply noise caused by the power supply switching.

    摘要翻译： 本发明的位线过驱动电路包括VBLH电位产生电路，其相对于用于驱动读出放大器的VBLH电源线产生位线最终电位，电荷调整电容C，用于向VBLH提供过驱动电位的晶体管 电源线和用于将PCS节点连接到VBLH电源线的晶体管。 从过驱动电位预充电到VBLH电源线的电荷在连接到VBLH电源线的上述电路元件的电容，位线电容和单元电容器的电容之间共享，以便 形成基本上一个系统的VBLH电源，从而避免由电源切换引起的电源噪声的产生。

    Fuse circuit using capacitors as fuse elements
    52.
    发明授权
    Fuse circuit using capacitors as fuse elements 失效

    公开(公告)号：US06657531B2

    公开(公告)日：2003-12-02

    申请号：US10026230

    申请日：2001-12-21

    申请人： Tohru Kimura ,  Masaru Koyanagi

    发明人： Tohru Kimura ,  Masaru Koyanagi

    IPC分类号： H01H8530

    CPC分类号： G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fuse circuit includes electrical fuse elements which are commonly connected at one-side ends, a voltage generating section and a readout section. The voltage generating section is configured to selectively apply program voltage for destroying the electrical fuse element and read voltage for reading out the destructive/nondestructive states of the electrical fuse elements to a common connection node of the one-side ends of the electrical fuse elements. The readout section is configured to read out the destructive/nondestructive states of the electrical fuse elements from the other ends of the electrical fuse elements when the read voltage is applied to the common connection node from the voltage generating section.

    Semiconductor memory device
    53.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06349069B2

    公开(公告)日：2002-02-19

    申请号：US09879145

    申请日：2001-06-13

    申请人： Kenichi Matoba ,  Masaru Koyanagi

    发明人： Kenichi Matoba ,  Masaru Koyanagi

    IPC分类号： G11C800

    CPC分类号： G11C8/12

    摘要： A semiconductor memory device comprises a first core section including a plurality of memory cell arrays, a second core section including a plurality of memory cell arrays and provided below the first core section, a third core section including a plurality of memory cell arrays and provided in a right side of the first core section, and a fourth core section including a plurality of memory cell arrays and provided in a right side of the second core section, wherein at least a part of the memory cell arrays of the first core section and at least a part of the memory cell arrays of the fourth core section are simultaneously activated, and at least a part, of the memory cell arrays of the second core section and at least a part of the memory cell arrays of the third core section are simultaneously activated.

    摘要翻译： 半导体存储器件包括：第一芯部分，包括多个存储单元阵列;第二芯部分，包括多个存储单元阵列并且设置在第一芯部下;第三核心部分，包括多个存储单元阵列， 第一芯部的右侧，以及包括多个存储单元阵列并设置在第二芯部的右侧的第四芯部，其中，第一芯部的存储单元阵列的至少一部分和 同时激活第四核心部分的存储单元阵列的至少一部分，并且第二核心部分的存储单元阵列和第三核心部分的至少一部分存储单元阵列的至少一部分同时 活性。

    Semiconductor integrated circuit device with output circuit
    54.
    发明授权
    Semiconductor integrated circuit device with output circuit 失效
    具有输出电路的半导体集成电路器件

    公开(公告)号：US5955891A

    公开(公告)日：1999-09-21

    申请号：US572381

    申请日：1995-12-14

    申请人： Eiichi Makino ,  Masaru Koyanagi

    发明人： Eiichi Makino ,  Masaru Koyanagi

    IPC分类号： G05F1/56 ,  G05F3/24 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0185

    CPC分类号： H03K19/00361

    摘要： The control voltage .phi.1 outputted by the control voltage generating circuit 1 is at a low level in a range where an external supply voltage Vcc is lower than the threshold value of the transistor P1, but increases continuously in analog manner when the external supply voltage Vcc rises. After having matched the external supply voltage Vcc, the control voltage .phi.1 increases in the same way as the external supply voltage Vcc. By use of the control voltage provided with the characteristics as described above for an output circuit, controlled is the gate of a transistor P4 of a low-voltage operating output section 6 operative only at a voltage lower than a predetermined value. The transistor P2 of a full-voltage operating output section 5 of the output circuit is always operative on the basis of the control signal .phi.H of the data output control circuit 3. When the external supply voltage is low below the predetermined value, the transistor P4 is perfectly turned on, so that the conductance thereof increases. In the semiconductor integrated circuit device operative on the basis of a plurality of supply voltages, it is possible to prevent the operation margin from being reduced near the switching point of the gate voltages of the driving transistors and the data output transistors.

    摘要翻译： 控制电压产生电路1输出的控制电压phi 1在外部电源电压Vcc低于晶体管P1的阈值的范围内处于低电平，但是当外部电源电压Vcc 上升。 在匹配外部电源电压Vcc之后，控制电压phi 1以与外部电源电压Vcc相同的方式增加。 通过使用具有如上所述的用于输出电路的特性的控制电压，受控的是低电压工作输出部分6的晶体管P4的栅极仅在低于预定值的电压下工作。 输出电路的全压工作输出部分5的晶体管P2总是基于数据输出控制电路3的控制信号phi H而工作。当外部电源电压低于预定值时，晶体管 P4完全打开，使其电导增加。 在基于多个电源电压工作的半导体集成电路装置中，可以防止在驱动晶体管和数据输出晶体管的栅极电压的切换点附近的操作余量减小。

    Semiconductor memory device
    55.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5640355A

    公开(公告)日：1997-06-17

    申请号：US471507

    申请日：1995-06-06

    申请人： Kazuyoshi Muraoka ,  Masaru Koyanagi ,  Yoshiaki Takeuchi

    发明人： Kazuyoshi Muraoka ,  Masaru Koyanagi ,  Yoshiaki Takeuchi

    IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C7/12 ,  G11C11/401 ,  G11C11/409 ,  G11C7/00

    CPC分类号： G11C7/065 ,  G11C7/12

    摘要： A semiconductor memory device including a memory cell array, bit lines, and sense amplifier groups. The memory cell array is composed of a plurality of memory cells arranged roughly in a matrix pattern. A plurality of the memory cells arranged in a row are activated in response to a row address decode signal. A pair of the bit lines are provided for each column. The data of the corresponding activated memory cells are transmitted to the bit line pair. Each of the sense amplifier groups has n-units of sense amplifiers each connected to the bit line pair, to sense and amplify data read to the bit line pair connected thereto. The respective reference potential terminals of the sense amplifiers of each of the sense amplifier groups are connected to a single common node which can be connected to a reference potential via a sense amplifier activating transistor turned on in response to a row address signal. The sense amplifiers can be operated at high speed, while preventing erroneous operation, because the wiring resistances and the parasitic capacitances of the common source node of the sense amplifiers can be reduced.

    摘要翻译： 一种包括存储单元阵列，位线和读出放大器组的半导体存储器件。 存储单元阵列由大致矩阵排列的多个存储单元构成。 响应于行地址解码信号，激活了排成行的多个存储单元。 为每列提供一对位线。 相应的激活的存储器单元的数据被发送到位线对。 读出放大器组中的每一个具有各自连接到位线对的读出放大器的n个单元，以检测和放大读取到与其连接的位线对的数据。 每个读出放大器组的读出放大器的相应参考电位端子连接到单个公共节点，该公共节点可以响应于行地址信号经由读出放大器激活晶体管导通而连接到参考电位。 由于读出放大器的公共源节点的布线电阻和寄生电容可以减小，所以读出放大器可以高速操作，同时防止错误的操作。

    Semiconductor integrated circuit with sense amplifier control circuit
    56.
    发明授权
    Semiconductor integrated circuit with sense amplifier control circuit 失效
    半导体集成电路与读出放大器控制电路

    公开(公告)号：US5570047A

    公开(公告)日：1996-10-29

    申请号：US298837

    申请日：1994-08-31

    申请人： Eiichi Makino ,  Masaru Koyanagi ,  Kazuyoshi Muraoka

    发明人： Eiichi Makino ,  Masaru Koyanagi ,  Kazuyoshi Muraoka

    IPC分类号： G11C11/409 ,  G11C5/14 ,  H03K5/153 ,  G11C7/00

    CPC分类号： G11C5/147

    摘要： A semiconductor integrated circuit includes memory cell blocks having memory cells arranged in matrix, sense amplifiers, each located adjacent to the memory cells, and sense amplifier control circuits, each of the sense amplifier control circuit being located on outside of the memory cell block. The sense amplifier control circuit has a standard voltage generating circuit and a control circuit for receiving the standard voltage and for transferring a driver signal to the sense amplifier to control the charging ability of the sense amplifier. The source voltage has three voltage regions, first, intermediate, and second regions. In the first voltage region, the potential of the driver signal increases with the increase of the source voltage. In the intermediate voltage region (2.7 to 3 Volt), the potential of the driver signal is changed oppose to the change of the source voltage, and in the second voltage region, the potential of the driver signal decreases with the increase of the source voltage.

    摘要翻译： 半导体集成电路包括具有排列成矩阵的存储单元的存储单元块，每个位于与存储单元相邻的读出放大器，以及读出放大器控制电路，每个读出放大器控制电路位于存储单元块的外部。 读出放大器控制电路具有标准电压发生电路和用于接收标准电压并将驱动器信号传送到读出放大器以控制读出放大器的充电能力的控制电路。 源电压具有三个电压区域，第一，中间和第二区域。 在第一电压区域中，驱动信号的电位随源电压的增加而增加。 在中间电压区域（2.7〜3伏特）中，驱动信号的电位相对于源极电压的变化而变化，在第二电压区域中，驱动信号的电位随着源极电压的增加而减小 。

    Semiconductor device provided with sense circuits
    59.
    发明授权
    Semiconductor device provided with sense circuits 失效
    设置有感测电路的半导体器件

    公开(公告)号：US5341013A

    公开(公告)日：1994-08-23

    申请号：US905661

    申请日：1992-06-29

    申请人： Masaru Koyanagi ,  Minoru Yamda

    发明人： Masaru Koyanagi ,  Minoru Yamda

    IPC分类号： G11C11/419 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L27/02

    CPC分类号： H01L27/088

    摘要： A semiconductor device provided with a plurality of sense circuits, each sense circuit including a pair of MOS transistors such that their sources are commonly connected, and that the drain of one transistor and the gate of the other transistor are cross-coupled each other to, thus, sense a difference between potentials applied to the respective gates. The paired transistors respectively include one transistor regions, and are disposed with their source regions being shared among the plurality of sense circuits. These sense circuits are disposed in a manner to share the source regions of the respective transistors. When elimination of only isolation between sense circuits meets with a required miniaturization of the device, paired transistors constituting sense circuits may include two transistor regions or more connected in parallel, respectively.

    摘要翻译： 一种设置有多个感测电路的半导体器件，每个感测电路包括一对MOS晶体管，使得它们的源极共同连接，并且一个晶体管的漏极和另一个晶体管的栅极彼此交叉耦合， 因此，感测施加到各个门的电位之间的差异。 成对晶体管分别包括一个晶体管区域，并且被布置成它们的源极区域在多个感测电路之间共享。 这些感测电路以共享各个晶体管的源极区域的方式设置。 当消除感测电路之间的仅隔离器件满足设备所需的小型化时，构成感测电路的成对晶体管可以分别包括两个或多个并联连接的晶体管区域。