公开(公告)号：US5087956A

公开(公告)日：1992-02-11

申请号：US358261

申请日：1989-05-30

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Kotaro Nishimura ,  Sho Yamamoto ,  Nobuyoshi Tanimura

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Kotaro Nishimura ,  Sho Yamamoto ,  Nobuyoshi Tanimura

IPC分类号： H01L21/02 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L28/20 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/904

摘要： An SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into at least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.

摘要翻译： 包括具有高电阻负载元件的存储单元的SRAM。 负载元件由多晶硅膜形成，并且为了增加使用负载元件形成的寄生MISFET的阈值电压作为其沟道区，将杂质引入到多晶硅膜的至少一部分中。 或者，多晶硅膜的沉积在相对高的温度下进行，从而防止流过负载元件的电流的任何增加，从而降低SRAM中的功率消耗。

公开(公告)号：US5079611A

公开(公告)日：1992-01-07

申请号：US599455

申请日：1990-10-18

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Makoto Motoyoshi ,  Osamu Minato

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Makoto Motoyoshi ,  Osamu Minato

IPC分类号： G11C11/34 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/10 ,  H01L27/11

CPC分类号： H01L27/1085 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/904

摘要： Herein disclosed is a semiconductor integrated circuit device having a SRAM, in which two MISFETs of a flip-flop circuit of a memory cell are connected directly with an n.sup.+ -type drain region so that they are cross coupled; and in which a p.sup.+ -type semiconductor region is formed below a direct contact part by making use of the mask used in the step of forming contact holes for the direct contact part. The p.sup.+ -type semiconductor region aids as a barrier to prevent soft errors of the SRAM due to .alpha.-particles.

摘要翻译： 这里公开了具有SRAM的半导体集成电路器件，其中存储单元的触发器电路的两个MISFET直接与n +型漏极区域连接，使得它们交叉耦合; 并且其中通过利用形成用于直接接触部分的接触孔的步骤中使用的掩模，在直接接触部分的下面形成p +型半导体区域。 p +型半导体区域有助于防止由于α-粒子而导致的SRAM的软错误。

公开(公告)号：US5034797A

公开(公告)日：1991-07-23

申请号：US497182

申请日：1990-03-22

申请人： Toshiaki Yamanaka ,  Yoshio Sakai ,  Takashi Hashimoto ,  Takashi Nishida ,  Satoshi Meguro ,  Shuji Ikeda ,  Eiji Takeda

发明人： Toshiaki Yamanaka ,  Yoshio Sakai ,  Takashi Hashimoto ,  Takashi Nishida ,  Satoshi Meguro ,  Shuji Ikeda ,  Eiji Takeda

IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/904

摘要： A semiconductor device having a CMIS structure for forming a static random access memory is disclosed which device can increase the packing density of the memory and reduce the stand-by power thereof. In this semiconductor device, a first MISFET of a first conductivity type is formed on and a substrate, a second MISFET of a second conductivity type is formed over the first MISFET with a first insulating film therebetween to form a stacked CMIS structure. The second MISFET is made up of a first conductive film, a second insulating film and a second conductive film, with the source, drain and channel regions of the second MISFET being formed in the first conductive film. A first resistive drain region is formed between the channel and drain regions of the first conductive film so that an impurity of the second conductivity type is contained in the first resistive drain region at a lower concentration than in the drain region, or the first resistive drain region is substantially undoped. The first resistive drain region is disposed over the gate electrode of the first MISFET, and the gate insulating film and gate electrode of the second MISFET are formed of the second insulating film and the second conductive film, respectively. In a case where a semiconductor memory device having a static random access memory cell which is provided with a flip-flop circuit of the stacked CMIS type, is formed, a pair of first MISFET's and a pair of third MISFET's of the first conductivity type are formed on the substrate, and the second MISFET is formed on one MISFET of the first MISFET's and the third MISFET's.

摘要翻译： 公开了具有用于形成静态随机存取存储器的CMIS结构的半导体器件，其可以增加存储器的堆积密度并降低其待机功率。 在该半导体器件中，在基板上形成第一导电型的第一MISFET，在第一MISFET上形成第二导电类型的第二MISFET，其间具有第一绝缘膜，以形成层叠的CMIS结构。 第二MISFET由第一导电膜，第二绝缘膜和第二导电膜构成，第二MISFET的源极，漏极和沟道区形成在第一导电膜中。 在第一导电膜的沟道和漏极区之间形成第一电阻漏极区，使得第一导电类型的杂质以比漏极区域低的浓度包含在第一电阻漏极区域中，或者第一电阻漏极 区域基本上未掺杂。 第一电阻漏极区域设置在第一MISFET的栅电极之上，并且第二MISFET的栅极绝缘膜和栅极电极分别由第二绝缘膜和第二导电膜形成。 在具有设置有层叠CMIS型触发电路的静态随机存取存储单元的半导体存储器件的情况下，形成一对第一MISFET和第一导电类型的一对第三MISFET 并且第一MISFET形成在第一MISFET和第三MISFET的一个MISFET上。

公开(公告)号：US4912674A

公开(公告)日：1990-03-27

申请号：US310353

申请日：1989-02-14

申请人： Youichi Matsumoto ,  Ryuuji Shibata ,  Isamu Kobayashi ,  Satoshi Meguro ,  Kouichi Nagasawa ,  Hideo Meguro ,  Hisahiro Moriuchi ,  Masahiro Ogata ,  Kikuo Sakai ,  Toshifumi Takeda

发明人： Youichi Matsumoto ,  Ryuuji Shibata ,  Isamu Kobayashi ,  Satoshi Meguro ,  Kouichi Nagasawa ,  Hideo Meguro ,  Hisahiro Moriuchi ,  Masahiro Ogata ,  Kikuo Sakai ,  Toshifumi Takeda

IPC分类号： G11C17/12 ,  H01L27/112

CPC分类号： H01L27/112 ,  G11C17/126

摘要： A mask-programmed ROM includes depletion type load MOSFETs provided between data lines in a memory array and a power supply voltage, the MOSFETs having a ground potential of the circuit applied to their gates. Reading of data is carried out by an amplifying MOSFET which supplies a current to a selected data line through a depletion type MOSFET which is supplied at its gate with the circuit ground potential. Thus, bias voltages which are respectively applied to the data lines and a sense amplifier which receives a signal read out from a selected data line are made equal to each other, thereby achieving a high-speed read operation.

摘要翻译： 掩模编程的ROM包括在存储器阵列中的数据线和电源电压之间提供的耗尽型负载MOSFET，MOSFET具有施加到其栅极的电路的接地电位。 数据的读取由放大MOSFET进行，该放大MOSFET通过在其栅极处提供电路接地电位的耗尽型MOSFET向所选择的数据线提供电流。 因此，分别施加到数据线的偏置电压和接收从所选择的数据线读出的信号的读出放大器彼此相等，从而实现高速读取操作。

公开(公告)号：US4890148A

公开(公告)日：1989-12-26

申请号：US218486

申请日：1988-07-07

申请人： Shuji Ikeda ,  Kouichi Nagasawa ,  Satoshi Meguro ,  Sho Yamamoto

发明人： Shuji Ikeda ,  Kouichi Nagasawa ,  Satoshi Meguro ,  Sho Yamamoto

IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L23/528 ,  H01L27/11

CPC分类号： G11C11/4125 ,  H01L23/528 ,  H01L27/11 ,  H01L27/1112 ,  H01L2924/0002

摘要： A static RAM exhibiting a high reliability and suited to a higher density of integration is disclosed. In each memory cell of this static RAM, the cross coupling of a flip-flop circuit is made by gate electrodes of MISFETs constituting this flip-flop circuit. In addition, a source line is formed by the same step as that of a word line. A resistance value of a polycrystalline silicon layer which is a load resistor is changed in accordance with information to be stored. Furthermore, semiconductor regions for preventing soft errors attributed to alpha particles etc. are formed under the MISFETs constituting the flip-flop circuit, so that the channels are not adversely affected.

摘要翻译： 公开了具有高可靠性并且适合于更高密度集成度的静态RAM。 在该静态RAM的每个存储单元中，触发器电路的交叉耦合由构成该触发器电路的MISFET的栅电极构成。 此外，源极线通过与字线的步骤相同的步骤形成。 作为负载电阻的多晶硅层的电阻值根据要存储的信息而改变。 此外，在构成触发电路的MISFET之下形成用于防止归因于α粒子等的软误差的半导体区域，使得通道不受不利影响。

公开(公告)号：US4841481A

公开(公告)日：1989-06-20

申请号：US225467

申请日：1988-07-28

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Kotaro Nishimura ,  Sho Yamamoto ,  Nobuyoshi Tanimura

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Kotaro Nishimura ,  Sho Yamamoto ,  Nobuyoshi Tanimura

IPC分类号： H01L21/02 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L28/20 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/903

摘要： An SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into a least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.

摘要翻译： 包括具有高电阻负载元件的存储单元的SRAM。 负载元件由多晶硅膜形成，并且为了增加使用负载元件形成的寄生MISFET的阈值电压作为其沟道区域，将杂质引入到多晶硅膜的至少一部分中。 或者，多晶硅膜的沉积在相对高的温度下进行，从而防止流过负载元件的电流的任何增加，从而降低SRAM中的功率消耗。

公开(公告)号：US4774203A

公开(公告)日：1988-09-27

申请号：US899404

申请日：1986-08-22

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Kotaro Nishimura ,  Sho Yamamoto ,  Nobuyoshi Tanimura

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Kotaro Nishimura ,  Sho Yamamoto ,  Nobuyoshi Tanimura

IPC分类号： H01L21/02 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/425 ,  H01L21/38

CPC分类号： H01L28/20 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/903

摘要： A method of making a static random-access memory device or SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into at least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.

摘要翻译： 一种制造静态随机存取存储器件或包括具有高电阻负载元件的存储单元的SRAM的方法。 负载元件由多晶硅膜形成，并且为了增加使用负载元件形成的寄生MISFET的阈值电压作为其沟道区，将杂质引入到多晶硅膜的至少一部分中。 或者，多晶硅膜的沉积在相对高的温度下进行，从而防止流过负载元件的电流的任何增加，从而降低SRAM中的功率消耗。

公开(公告)号：US4768076A

公开(公告)日：1988-08-30

申请号：US774705

申请日：1985-09-11

申请人： Masaaki Aoki ,  Toshiaki Masuhara ,  Terunori Warabisako ,  Shoji Hanamura ,  Yoshio Sakai ,  Seiichi Isomae ,  Satoshi Meguro ,  Shuji Ikeda

发明人： Masaaki Aoki ,  Toshiaki Masuhara ,  Terunori Warabisako ,  Shoji Hanamura ,  Yoshio Sakai ,  Seiichi Isomae ,  Satoshi Meguro ,  Shuji Ikeda

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L27/092 ,  H01L29/04 ,  H01L27/04

CPC分类号： H01L29/045 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/0922

摘要： A CMOS IC is formed on a semiconductor crystalline surface having a plane azimuth (110) or (023), or of a plane azimuth close thereto (plane azimuth substantially in parallel with the above-mentioned planes), in order to increase the speed of operation.At low temperatures, dependency of the carrier mobility upon the plane azimuth becomes more conspicuous as shown in FIG. 1, and the difference of mobility is amplified depending upon the planes. Therefore, employment of the above-mentioned crystalline planes helps produce a great effect when the CMOS device is to be operated at low temperature (e.g., 100.degree. K. or lower), and helps operate the device at high speeds.

摘要翻译： 在具有平面方位（110）或（023）或靠近其的平面方位（与上述平面平行的方位角）的半导体晶体表面上形成CMOS IC，以便提高 操作。 在低温下，载流子迁移率对平面方位角的依赖性变得更显着，如图3所示。 1，并且根据平面放大移动性的差异。 因此，当CMOS器件在低温（例如100°K或更低）下工作时，使用上述晶面有助于产生很大的效果，并且有助于高速操作器件。

公开(公告)号：US4199778A

公开(公告)日：1980-04-22

申请号：US843366

申请日：1977-10-19

申请人： Toshiaki Masuhara ,  Tokumasa Yasui ,  Yoshio Sakai ,  Joh Nakajima ,  Yasunobu Kosa ,  Satoshi Meguro ,  Masaharu Kubo

发明人： Toshiaki Masuhara ,  Tokumasa Yasui ,  Yoshio Sakai ,  Joh Nakajima ,  Yasunobu Kosa ,  Satoshi Meguro ,  Masaharu Kubo

IPC分类号： H01L21/763 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/3215 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L29/04 ,  H01L23/48 ,  H01L29/44

CPC分类号： H01L21/32155 ,  H01L21/76889 ,  H01L23/53271 ,  H01L2924/0002

摘要： In a semiconductor integrated circuit having polycrystalline silicon interconnections and metal interconnections, a low resistance layer, containing impurities to a high concentration for the polycrystalline silicon interconnections, is formed in predetermined parts of an undoped polycrystalline silicon layer which is deposited on a first insulator film on a semiconductor substrate, a second insulator film is deposited on the polycrystalline silicon layer under the state under which the undoped parts are left at least around through-holes to be formed, and the metal interconnections at least parts of which run in a direction intersecting the polycrystalline silicon interconnections are provided on the second insulator film, the necessary contacts between the metal interconnections and the polycrystalline silicon interconnections being made through the through-holes provided in the second insulator film in correspondence with the intersecting parts of both the interconnections.

摘要翻译： 在具有多晶硅互连和金属互连的半导体集成电路中，在未掺杂的多晶硅层的预定部分中形成在多晶硅互连中含有高浓度的杂质的低电阻层，其沉积在第一绝缘膜上 半导体衬底，第二绝缘膜沉积在多晶硅层上，在未被掺杂的部分至少留在待形成的通孔周围的状态下，并且其至少部分的金属互连在与 多晶硅互连设置在第二绝缘膜上，金属互连和多晶硅互连之间的必要接触通过设置在第二绝缘膜中的通孔形成，与两个互连的相交部分相对应。

公开(公告)号：US06538847B2

公开(公告)日：2003-03-25

申请号：US09764351

申请日：2001-01-19

申请人： Satoshi Meguro ,  Shigeo Fujii ,  Hiroyuki Mima ,  Toshihiro Ifuka

发明人： Satoshi Meguro ,  Shigeo Fujii ,  Hiroyuki Mima ,  Toshihiro Ifuka

IPC分类号： G11B5147

CPC分类号： B82Y10/00 ,  G11B5/3116 ,  G11B5/312 ,  G11B5/313 ,  G11B5/3163 ,  G11B5/3967

摘要： An inductive magnetic head used for high-density recording having such a construction that prevents magnetic leakage near a magnetic pole at the tip of the magnetic core and reduces magnetic resistance or reluctance at an upper magnetic core front portion is disclosed. An upper magnetic core facing a lower magnetic core with a non-magnetic gap layer interposed therebetween comprises an upper magnetic core front portion near a magnetic pole, and an upper magnetic core rear portion at the rear portion. The front portion has a parallel portion having a width almost equal to the track width extending from the magnetic pole toward the rear end of the front portion, and a sector at the rear of an apex. The front portion has a non-magnetic gap with the lower magnetic core at an area between the magnetic pole and the apex, and the gap between the front portion and the lower magnetic core is wider than the magnetic gap at the rear of the apex. The tip portion of the upper magnetic core rear portion is overlapped and connected to the upper magnetic core front portion on the medium-facing surface side of the apex, extending therefrom to the upper part of a coil and a coil insulating layer.

摘要翻译： 公开了一种用于高密度记录的感应磁头，其具有防止在磁芯顶端附近的磁极附近的磁泄漏并降低上磁芯前部的磁阻或磁阻的结构。 面对具有介于其间的非磁隙层的下磁芯的上磁芯包括在磁极附近的上磁芯前部和在后部的上磁芯后部。 前部具有平行部分，该平行部分的宽度几乎等于从磁极向前部的后端延伸的轨道宽度，以及在顶点后部的扇形部分。 前部在磁极和顶点之间的区域处具有与下磁芯的非磁性间隙，并且前部和下磁芯之间的间隙比顶点后部的磁隙宽。 上部磁芯后部的前端部与顶点的面向中间的表面侧的上部磁芯前部重叠并连接，从而向上延伸到线圈的上部和线圈绝缘层。