公开(公告)号：US5087956A

公开(公告)日：1992-02-11

申请号：US358261

申请日：1989-05-30

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Kotaro Nishimura ,  Sho Yamamoto ,  Nobuyoshi Tanimura

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Kotaro Nishimura ,  Sho Yamamoto ,  Nobuyoshi Tanimura

IPC分类号： H01L21/02 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L28/20 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/904

摘要： An SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into at least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.

摘要翻译： 包括具有高电阻负载元件的存储单元的SRAM。 负载元件由多晶硅膜形成，并且为了增加使用负载元件形成的寄生MISFET的阈值电压作为其沟道区，将杂质引入到多晶硅膜的至少一部分中。 或者，多晶硅膜的沉积在相对高的温度下进行，从而防止流过负载元件的电流的任何增加，从而降低SRAM中的功率消耗。

公开(公告)号：US4841481A

公开(公告)日：1989-06-20

申请号：US225467

申请日：1988-07-28

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Kotaro Nishimura ,  Sho Yamamoto ,  Nobuyoshi Tanimura

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Kotaro Nishimura ,  Sho Yamamoto ,  Nobuyoshi Tanimura

IPC分类号： H01L21/02 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L28/20 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/903

摘要： An SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into a least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.

摘要翻译： 包括具有高电阻负载元件的存储单元的SRAM。 负载元件由多晶硅膜形成，并且为了增加使用负载元件形成的寄生MISFET的阈值电压作为其沟道区域，将杂质引入到多晶硅膜的至少一部分中。 或者，多晶硅膜的沉积在相对高的温度下进行，从而防止流过负载元件的电流的任何增加，从而降低SRAM中的功率消耗。

公开(公告)号：US4774203A

公开(公告)日：1988-09-27

申请号：US899404

申请日：1986-08-22

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Kotaro Nishimura ,  Sho Yamamoto ,  Nobuyoshi Tanimura

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Kotaro Nishimura ,  Sho Yamamoto ,  Nobuyoshi Tanimura

IPC分类号： H01L21/02 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/425 ,  H01L21/38

CPC分类号： H01L28/20 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/903

摘要： A method of making a static random-access memory device or SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into at least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.

摘要翻译： 一种制造静态随机存取存储器件或包括具有高电阻负载元件的存储单元的SRAM的方法。 负载元件由多晶硅膜形成，并且为了增加使用负载元件形成的寄生MISFET的阈值电压作为其沟道区，将杂质引入到多晶硅膜的至少一部分中。 或者，多晶硅膜的沉积在相对高的温度下进行，从而防止流过负载元件的电流的任何增加，从而降低SRAM中的功率消耗。

公开(公告)号：US4300213A

公开(公告)日：1981-11-10

申请号：US89745

申请日：1979-10-31

申请人： Nobuyoshi Tanimura ,  Hiroshi Fukuta ,  Kotaro Nishimura ,  Tokumasa Yasui

发明人： Nobuyoshi Tanimura ,  Hiroshi Fukuta ,  Kotaro Nishimura ,  Tokumasa Yasui

IPC分类号： G11C11/412 ,  G11C11/417 ,  H03K19/0185 ,  H03K19/0944 ,  G11C7/00

CPC分类号： G11C11/412 ,  G11C11/417 ,  H03K19/018507 ,  H03K19/09443

摘要： Digit lines, connected to the input and output terminals of a memory cell composed of MISFETs, are coupled to common data lines through a switching circuit which is controlled by a decoder circuit. There is also connected with the digit lines a load which is composed of a plurality of enhancement mode MISFETs connected in series in the diode form. The high level of the signals at the digit lines is lowered by the action of the load means. In response to the reduction in the potentials at the digit lines, the switching means is rendered conductive at an early rise time of control signals. As a result, the operating speed of the memory circuit can be increased.

摘要翻译： 连接到由MISFET组成的存储单元的输入和输出端的数字线通过由解码器电路控制的开关电路耦合到公共数据线。 还与数字线连接由多个以二极管形式串联连接的多个增强型MISFET组成的负载。 数字线上的高电平信号通过负载装置的作用而降低。 响应于数字线上的电位降低，开关装置在控制信号的早期上升时间被导通。 结果，可以提高存储电路的工作速度。

公开(公告)号：US5159260A

公开(公告)日：1992-10-27

申请号：US4307

申请日：1987-01-07

申请人： Kanji Yoh ,  Osamu Yamashiro ,  Satoshi Meguro ,  Koichi Nagasawa ,  Kotaro Nishimura ,  Harumi Wakimoto ,  Kazutaka Narita

发明人： Kanji Yoh ,  Osamu Yamashiro ,  Satoshi Meguro ,  Koichi Nagasawa ,  Kotaro Nishimura ,  Harumi Wakimoto ,  Kazutaka Narita

IPC分类号： G05F3/24 ,  G11C5/14 ,  G11C11/411 ,  G11C11/417 ,  H01L27/088 ,  H01L29/49 ,  H03F3/45 ,  H03K3/0231 ,  H03K3/0233 ,  H03K3/3565 ,  H03K5/24 ,  H03K19/003 ,  H03K19/0185

CPC分类号： G11C11/4113 ,  G05F3/245 ,  G11C11/417 ,  G11C5/143 ,  G11C5/147 ,  H01L27/088 ,  H01L29/4983 ,  H03F3/45179 ,  H03F3/45744 ,  H03F3/45748 ,  H03K19/00384 ,  H03K19/018507 ,  H03K19/018514 ,  H03K3/0231 ,  H03K3/02337 ,  H03K3/3565 ,  H03K5/2481 ,  H03F2203/45394

摘要： This reference voltage generator device detects a voltage corresponding to an energy gap of a semiconductor, or a voltage of a value close thereto, or a voltage based on an energy level of a semiconductor, and generates the detected voltage as a reference voltage. The reference voltage is generated by detecting a difference of threshold voltages of first and second insulated gate field-effect transistors (IGFETs). Gate electrodes of the first and second IGFETs are formed on gate insulating films which are formed on different surface areas of an identical semiconductor substrate under substantially the same conditions. The gate electrodes of the first and second IGFETs are respectively made of two semiconductors which are selected from among a semiconductor of a first conductivity type, a semiconductor of a second conductivity type and an intrinsic semiconductor made of an identical semiconductor material, and which have Fermi energy levels of values different from each other. The channels of the first and second IGFETs have an identical conductivity type. On the basis of a self-alignment structure, at least those parts of first and second polycrystalline semiconductor regions being the gate electrodes of the first and second IGFETs which are proximate to source and drain regions are doped with the same impurity as that of the source and drain regions, and a central part of one of the first and second polycrystalline semiconductor regions is doped with an impurity of a selected one of the first conductivity type and the second conductivity type.

摘要翻译： 该参考电压发生器装置检测与半导体的能隙对应的电压或与其接近的值的电压或基于半导体的能级的电压，并产生检测电压作为参考电压。 通过检测第一和第二绝缘栅极场效应晶体管（IGFET）的阈值电压的差异来产生参考电压。 第一和第二IGFET的栅电极形成在基本相同条件下形成在相同半导体衬底的不同表面区域上的栅极绝缘膜上。 第一和第二IGFET的栅电极分别由选自第一导电类型的半导体，第二导​​电类型的半导体和由相同的半导体材料制成的本征半导体的两个半导体制成，并且具有费米 能量水平值彼此不同。 第一和第二IGFET的通道具有相同的导电类型。 基于自对准结构，至少第一和第二多晶半导体区域的那些部分是靠近源区和漏区的第一和第二IGFET的栅电极，其掺杂与源的相同杂质 和漏极区域，并且第一和第二多晶半导体区域之一的中心部分掺杂有选择的第一导电类型和第二导电类型的杂质。

公开(公告)号：US4641285A

公开(公告)日：1987-02-03

申请号：US640508

申请日：1984-08-13

申请人： Yukio Sasaki ,  Kotaro Nishimura ,  Osamu Minato

发明人： Yukio Sasaki ,  Kotaro Nishimura ,  Osamu Minato

IPC分类号： G11C8/08 ,  G11C29/00 ,  G11C29/04 ,  G11C11/40

CPC分类号： G11C29/78 ,  G11C8/08

摘要： The line change-over circuit suitable for the semiconductor memory having a redundancy memory column comprises a pair of transfer gate elements provided between a first node to which a first signal to be transmitted is supplied and a pair of transmission lines, first and second switch elements. The paired transfer gate elements are controlled on a switch in complementary manner each other according to a transfer signal. The first switch element is controlled on a switch according to the transfer signal, and the second switch element is controlled on a switch according to the first signal transmitted to one of the paired transmission lines. The first switch element turns one of the transmission lines to a fixed potential like ground potential when it is kept on, and the second switch element turns the other of the transmission lines to a fixed potential when it is kept on. The line change-over circuit in the above configuration is effective to prevent a floating state of the paired transmission lines.

摘要翻译： 适用于具有冗余存储器列的半导体存储器的线转换电路包括一对传输门元件，其设置在提供有待传输的第一信号的第一节点与一对传输线之间，第一和第二开关元件 。 成对的传输门元件根据传输信号彼此互补地控制在开关上。 第一开关元件根据传输信号被控制在开关上，并且第二开关元件根据传输到一对传输线之一的第一信号被控制在开关上。 当第一开关元件保持接通时，第一开关元件将其中一个传输线转到固定电位，如接地电位，并且当第二开关元件保持接通时，第二开关元件将另一个传输线转到固定电位。 上述配置中的线路切换电路有效地防止成对的传输线路的浮动状态。

公开(公告)号：US4261004A

公开(公告)日：1981-04-07

申请号：US929959

申请日：1978-08-01

申请人： Toshiaki Masuhara ,  Osamu Minato ,  Yoshio Sakai ,  Toshio Sasaki ,  Masaharu Kubo ,  Kotaro Nishimura ,  Tokumasa Yasui

发明人： Toshiaki Masuhara ,  Osamu Minato ,  Yoshio Sakai ,  Toshio Sasaki ,  Masaharu Kubo ,  Kotaro Nishimura ,  Tokumasa Yasui

IPC分类号： H03F1/52 ,  H01L21/02 ,  H01L21/822 ,  H01L23/62 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/78 ,  H03F1/42

CPC分类号： H01L28/20 ,  H01L27/0251 ,  H01L27/0288

摘要： On the surface of an insulating film formed on the surface of a semiconductor substrate on which an MOS type semiconductor device to be protected is formed, there are formed a first polycrystal silicon member having input and output terminals and a resistivity lower than 1 K.OMEGA./.quadrature. and a second polycrystalline silicon member having a resistivity lower than 1 K.OMEGA./.quadrature. and being maintained at a fixed potential. This second polycrystalline silicon member faces at least a part of the first silicon member with polycrystalline silicon of a resistivity higher than 100 K.OMEGA./.quadrature. interposed therebetween. The input terminal of the first polycrystalline silicon member is connected to an input pad of the MOS type semiconductor device to be protected and the output terminal of the first polycrystalline silicon member is connected to an input gate of the semiconductor device to be protected. The input gate of the semiconductor device is protected by utilizing the punch-through effect in the interior of the polycrystalline silicon having a resistivity higher than 100 K.OMEGA./.quadrature..

摘要翻译： 在形成有要形成有待保护的MOS型半导体器件的半导体衬底的表面上的绝缘膜的表面上形成有具有输入和输出端子的电阻率低于1KΩ的第一多晶硅元件， 并且具有电阻率低于1KΩ/□并且保持在固定电位的第二多晶硅部件。 该第二多晶硅部件面对第一硅部件的至少一部分，其中多晶硅的电阻率高于100KΩ，并插入其间。 第一多晶硅部件的输入端子连接到要被保护的MOS型半导体器件的输入焊盘，并且第一多晶硅部件的输出端子连接到待保护的半导体器件的输入栅极。 半导体器件的输入栅极通过利用电阻率高于100KΩ/□的多晶硅的内部的穿透效应来保护。

公开(公告)号：US4063118A

公开(公告)日：1977-12-13

申请号：US689816

申请日：1976-05-25

申请人： Kotaro Nishimura

发明人： Kotaro Nishimura

IPC分类号： G11C19/28 ,  G11C8/10 ,  H03K19/003 ,  H03K19/017 ,  H03K19/096 ,  H03K19/08 ,  G11C8/00 ,  G11C15/04 ,  H03K19/34

CPC分类号： H03K19/017 ,  G11C8/10 ,  H03K19/00315

摘要： In a multiplicity of NAND decoders, each comprises a dynamic ratioless circuit including a capacitor to be charged in response to a precharge pulse, an MOS logic circuit for discharging the capacitor by an address pulse in the non-selection mode, and first and second MOSFETs connected in series between a clock pulse terminal and ground. The first MOSFET conducts in response to the terminal voltage of the capacitor to transmit a clock pulse from its drain and supplies an output to a word line. The terminal voltage of the capacitor in one decoder is applied to the gate of the second MOSFET of another decoder and the word line output of the other decoder is grounded even during the discharging period of the capacitor in the non-selection mode of the other decoder, enabling a synchronous supply of the address and the clock pulses.

摘要翻译： 在多个NAND解码器中，每个都包括一个动态无量纲电路，其包括响应于预充电脉冲而被充电的电容器，用于以非选择模式的寻址脉冲放电电容器的MOS逻辑电路以及第一和第二MOSFET 在时钟脉冲端子和地之间串联连接。 第一个MOSFET响应于电容器的端子电压而导通，以从其漏极传输时钟脉冲，并将输出提供给字线。 一个解码器中的电容器的端子电压被施加到另一个解码器的第二个MOSFET的栅极，并且另一个解码器的字线输出甚至在另一个解码器的非选择模式下的电容器的放电期间也接地 ，能够同时提供地址和时钟脉冲。

公开(公告)号：US5359562A

公开(公告)日：1994-10-25

申请号：US684867

申请日：1991-04-15

申请人： Tokumasa Yasui ,  Shinji Shimizu ,  Kotaro Nishimura

发明人： Tokumasa Yasui ,  Shinji Shimizu ,  Kotaro Nishimura

IPC分类号： G11C11/412 ,  G11C11/418 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H03K19/0185 ,  G11C11/417 ,  G11C7/02

CPC分类号： G11C11/412 ,  G11C11/418 ,  H01L27/0688 ,  H01L27/0927 ,  H01L27/1112 ,  H03K19/01855 ,  H01L27/105 ,  Y10S257/904

摘要： A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of N-conductivity type, and a pair of load resistors of polycrystalline silicon respectively coupled to the pair of cross-coupled transistors. A peripheral circuit is also provided which is constituted by metal insulated gate field effect transistors having channels of the N-conductivity type and metal insulated gate field effect transistors having channels of P-conductivity type. The semiconductor memory device is formed in an N-type semiconductor substrate, and the pair of cross-coupled metal insulated gate field effect transistors of the memory cells are formed in a well region of P-type which forms a PN-junction with the semiconductor substrate to help reduce the susceptibility to soft errors.

摘要翻译： 提供了一种半导体存储器件，其具有多个存储单元，每个存储单元包括一对具有N-导电型通道的交叉耦合的金属绝缘栅场效应晶体管，以及分别耦合到所述一对的多晶硅的一对负载电阻器 交叉耦合晶体管。 还提供外围电路，其由具有N导电型通道的金属绝缘栅场效应晶体管和具有P导电型通道的金属绝缘栅场效应晶体管构成。 半导体存储器件形成在N型半导体衬底中，并且存储单元的一对交叉耦合金属绝缘栅场效应晶体管形成在与半导体形成PN结的P型阱区中 底物有助于降低软错误的易感性。

公开(公告)号：US4060740A

公开(公告)日：1977-11-29

申请号：US685925

申请日：1976-05-12

申请人： Kotaro Nishimura

发明人： Kotaro Nishimura

IPC分类号： G11C11/409 ,  G11C11/4091 ,  H03K3/356 ,  H03K5/003 ,  H03K5/18 ,  G11C11/40 ,  H03K3/286 ,  H03K3/353

CPC分类号： G11C11/4091 ,  H03K3/356017 ,  H03K3/356026 ,  H03K3/356069 ,  H03K5/003

摘要： In a sensing amplifier for a capacitive MISFET memory, the level of an output signal from the memory is shifted by a signal level shifting circuit and the level-shifted signal is applied to an input of the sensing amplifier to thereby provide a high speed operation.

摘要翻译： 在用于电容式MISFET存储器的感测放大器中，来自存储器的输出信号的电平被信号电平移位电路移位，并且电平移位信号被施加到感测放大器的输入，从而提供高速操作。