公开(公告)号：US20110318858A1

公开(公告)日：2011-12-29

申请号：US13220694

申请日：2011-08-30

申请人： Kuo-Lung Fang ,  Chien-Sen Weng ,  Chih-Wei Chao

发明人： Kuo-Lung Fang ,  Chien-Sen Weng ,  Chih-Wei Chao

IPC分类号： H01L33/44

CPC分类号： H01L33/387 ,  H01L33/382 ,  H01L33/44

摘要： A method for fabricating a light emitting diode chip is provided. Firstly, a semiconductor device layer is formed on a substrate. Afterwards, a current spreading layer is formed on a portion of the semiconductor device layer. Then, a current blocking layer and a passivation layer are formed on a portion of the semiconductor device layer not covered by the current spreading layer. Finally, a first electrode is formed on the current blocking layer and the current spreading layer. Moreover, a second electrode is formed on the semiconductor device layer.

公开(公告)号：US08058087B2

公开(公告)日：2011-11-15

申请号：US12356090

申请日：2009-01-20

申请人： Shine-Kai Tseng ,  Han-Tu Lin ,  Shiun-Chang Jan ,  Kuo-Lung Fang

发明人： Shine-Kai Tseng ,  Han-Tu Lin ,  Shiun-Chang Jan ,  Kuo-Lung Fang

IPC分类号： H01L21/338 ,  H01L31/112

CPC分类号： H01L27/1248 ,  H01L27/1288

摘要： A method for fabricating a TFT array substrate includes following steps. A gate pattern and a first pad pattern are formed on a substrate. A gate insulation layer and a semiconductor layer covering the two patterns are sequentially formed. A patterned photoresist layer having different resist blocks is formed, and patterns and thicknesses of the resist blocks in different regions are adjusted. The semiconductor layer and the gate insulation layer above the first pad pattern are removed through performing an etching process and reducing a thickness of the patterned photoresist layer. After removing the patterned photoresist layer, a source pattern, a drain pattern, and a second pad pattern electrically connected to the first pad pattern are formed. A patterned passivation layer is formed on the gate insulation layer and has a second opening exposing the source pattern or the drain pattern and a third opening exposing the second pad pattern.

摘要翻译： 制造TFT阵列基板的方法包括以下步骤。 在基板上形成栅极图案和第一焊盘图案。 依次形成覆盖这两个图案的栅绝缘层和半导体层。 形成具有不同抗蚀剂块的图案化光致抗蚀剂层，并且调整不同区域中的抗蚀剂块的图案和厚度。 通过执行蚀刻工艺并减小图案化光致抗蚀剂层的厚度来去除第一焊盘图案上方的半导体层和栅极绝缘层。 在去除图案化的光致抗蚀剂层之后，形成电连接到第一焊盘图案的源图案，漏极图案和第二焊盘图案。 图案化的钝化层形成在栅极绝缘层上，并且具有暴露源图案或漏极图案的第二开口和暴露第二焊盘图案的第三开口。

公开(公告)号：US20110159613A1

公开(公告)日：2011-06-30

申请号：US13046619

申请日：2011-03-11

申请人： Kuo-Lung Fang ,  Chien-Sen Weng ,  Chih-Wei Chao

发明人： Kuo-Lung Fang ,  Chien-Sen Weng ,  Chih-Wei Chao

IPC分类号： H01L33/48

CPC分类号： H01L33/44 ,  H01L33/387 ,  Y10S438/951

摘要： A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

公开(公告)号：US20110159612A1

公开(公告)日：2011-06-30

申请号：US13046576

申请日：2011-03-11

申请人： Kuo-Lung Fang ,  Chien-Sen Weng ,  Chih-Wei Chao

发明人： Kuo-Lung Fang ,  Chien-Sen Weng ,  Chih-Wei Chao

IPC分类号： H01L33/52

CPC分类号： H01L33/44 ,  H01L33/387 ,  Y10S438/951

摘要： A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

公开(公告)号：US07888190B2

公开(公告)日：2011-02-15

申请号：US12170620

申请日：2008-07-10

申请人： Kuo-Lung Fang ,  Wen-Ching Tsai ,  Yeong-Shyang Lee ,  Han-Tu Lin

发明人： Kuo-Lung Fang ,  Wen-Ching Tsai ,  Yeong-Shyang Lee ,  Han-Tu Lin

IPC分类号： H01L21/00

CPC分类号： H01L29/4908 ,  H01L29/66765

摘要： The invention discloses a switching element of a pixel electrode for a display device and methods for fabricating the same. A gate is formed on a substrate. A first copper silicide layer is formed on the gate. An insulating layer is formed on the first copper silicide layer. A semiconductor layer is formed on the insulating layer. A source and a drain are formed on the semiconductor layer. Moreover, a second copper silicide layer is sandwiched between the semiconductor layer and the source/drain.

摘要翻译： 本发明公开了一种用于显示装置的像素电极的开关元件及其制造方法。 栅极形成在基板上。 在栅极上形成第一铜硅化物层。 在第一硅化铜层上形成绝缘层。 在绝缘层上形成半导体层。 源极和漏极形成在半导体层上。 此外，第二硅化铜层夹在半导体层和源极/漏极之间。

公开(公告)号：US20100221494A1

公开(公告)日：2010-09-02

申请号：US12465655

申请日：2009-05-14

申请人： Chang-Ming Lu ,  Chih-Wei Chao ,  Te-Chung Wang ,  Kuo-Lung Fang ,  Chun-Jong Chang

发明人： Chang-Ming Lu ,  Chih-Wei Chao ,  Te-Chung Wang ,  Kuo-Lung Fang ,  Chun-Jong Chang

IPC分类号： B32B3/00 ,  H01L21/20

CPC分类号： H01L21/02647 ,  C30B25/02 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02433 ,  H01L21/02639 ,  Y10T428/24479

摘要： A method for forming a semiconductor layer includes following steps. First, an epitaxial substrate having at least a first growth region and at least a second growth region is provided. An area ratio of C plane to R plane in the first growth region is greater than 52/48. An epitaxial process is then performed on the epitaxial substrate to form a semiconductor layer. During the epitaxial process, a semiconductor material is selectively grown on the first growth region, and then the semiconductor material is laterally overgrown on the second growth region and covers the same.

摘要翻译： 形成半导体层的方法包括以下步骤。 首先，提供具有至少第一生长区和至少第二生长区的外延衬底。 第一生长区域中C面与R面的面积比大于52/48。 然后在外延衬底上进行外延工艺以形成半导体层。 在外延工艺期间，半导体材料选择性地生长在第一生长区域上，然后半导体材料在第二生长区域上横向长满而覆盖。

公开(公告)号：US20100213464A1

公开(公告)日：2010-08-26

申请号：US12775493

申请日：2010-05-07

申请人： Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

发明人： Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

IPC分类号： H01L33/16

CPC分类号： H01L27/124 ,  H01L27/1248 ,  H01L27/1288

摘要： An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.

摘要翻译： 设置在基板上的有源矩阵阵列结构包括第一图案化导电层，图案化栅极绝缘层，图案化半导体层，第二图案化导电层，图案化外涂层和透明导电层。 图案化栅极绝缘层具有暴露第一图案化导电层的一部分的第一开口。 图案化的半导体层设置在图案化的栅极绝缘层上。 第二图案化导电层设置在图案化的半导体层上。 图案化的外涂层具有暴露第一图案化导电层的一部分和第二图案化导电层的一部分的第二开口。 透明导电层完全设置在基板上。 设置在第一开口和第二开口中的透明导电层在基板和图案化外涂层之间的位置处断开。

公开(公告)号：US20100015742A1

公开(公告)日：2010-01-21

申请号：US12252370

申请日：2008-10-16

申请人： Kuo-Lung Fang ,  Chien-Sen Weng ,  Chih-Wei Chao

发明人： Kuo-Lung Fang ,  Chien-Sen Weng ,  Chih-Wei Chao

IPC分类号： H01L21/00

CPC分类号： H01L33/44 ,  H01L33/387 ,  Y10S438/951

摘要： A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

摘要翻译： 提供一种制造发光二极管芯片的方法。 在该方法中，应用半色调掩模处理，灰度色调处理或多色调掩模处理，并与剥离处理相结合，以进一步减少发光二极管芯片的处理步骤。 在本发明中，一些部件也可以通过相同的工艺同时形成，以减少发光二极管芯片的工艺步骤。 因此，本发明中提供的发光二极管的制造方法降低了用于制造发光二极管的成本和时间。

公开(公告)号：US20100009481A1

公开(公告)日：2010-01-14

申请号：US12356090

申请日：2009-01-20

申请人： Shine-Kai Tseng ,  Han-Tu Lin ,  Shiun-Chang Jan ,  Kuo-Lung Fang

发明人： Shine-Kai Tseng ,  Han-Tu Lin ,  Shiun-Chang Jan ,  Kuo-Lung Fang

IPC分类号： H01L21/336

CPC分类号： H01L27/1248 ,  H01L27/1288

摘要： A method for fabricating a TFT array substrate includes following steps. A gate pattern and a first pad pattern are formed on a substrate. A gate insulation layer and a semiconductor layer covering the two patterns are sequentially formed. A patterned photoresist layer having different resist blocks is formed, and patterns and thicknesses of the resist blocks in different regions are adjusted. The semiconductor layer and the gate insulation layer above the first pad pattern are removed through performing an etching process and reducing a thickness of the patterned photoresist layer. After removing the patterned photoresist layer, a source pattern, a drain pattern, and a second pad pattern electrically connected to the first pad pattern are formed. A patterned passivation layer is formed on the gate insulation layer and has a second opening exposing the source pattern or the drain pattern and a third opening exposing the second pad pattern.

摘要翻译： 制造TFT阵列基板的方法包括以下步骤。 在基板上形成栅极图案和第一焊盘图案。 依次形成覆盖这两个图案的栅绝缘层和半导体层。 形成具有不同抗蚀剂块的图案化光致抗蚀剂层，并且调整不同区域中的抗蚀剂块的图案和厚度。 通过执行蚀刻工艺并减小图案化光致抗蚀剂层的厚度来去除第一焊盘图案上方的半导体层和栅极绝缘层。 在去除图案化的光致抗蚀剂层之后，形成电连接到第一焊盘图案的源图案，漏极图案和第二焊盘图案。 图案化的钝化层形成在栅极绝缘层上，并且具有暴露源图案或漏极图案的第二开口和暴露第二焊盘图案的第三开口。

公开(公告)号：US20090325331A1

公开(公告)日：2009-12-31

申请号：US12233607

申请日：2008-09-19

申请人： Chih-Chun Yang ,  Ming-Yuan Huang ,  Han-Tu Lin ,  Chih-Hung Shih ,  Ta-Wen Liao ,  Kuo-Lung Fang ,  Chia-Chi Tsai

发明人： Chih-Chun Yang ,  Ming-Yuan Huang ,  Han-Tu Lin ,  Chih-Hung Shih ,  Ta-Wen Liao ,  Kuo-Lung Fang ,  Chia-Chi Tsai

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/44

CPC分类号： H01L27/1248 ,  H01L27/1288

摘要： A method for manufacturing a pixel structure is provided. First, a gate and a gate insulating layer are sequentially formed on the substrate. A channel layer and a second metal layer are sequentially formed on the gate insulating layer. The second metal layer is patterned to form a source and a drain by using a patterned photoresist layer formed thereon, wherein the source and the drain are disposed on a portion of the channel layer. The gate, the channel, the source and the drain form a thin film transistor. A passivation layer is formed on the patterned photoresist layer, the gate insulating layer and the thin film transistor. Then, the patterned photoresist layer is removed, such that the passivation layer thereon is removed simultaneously to form a patterned passivation layer and the drain is exposed. A pixel electrode is formed on the patterned passivation layer and the drain.

摘要翻译： 提供了一种用于制造像素结构的方法。 首先，在基板上依次形成栅极和栅极绝缘层。 沟道层和第二金属层依次形成在栅极绝缘层上。 图案化第二金属层以通过使用其上形成的图案化光致抗蚀剂层来形成源极和漏极，其中源极和漏极设置在沟道层的一部分上。 栅极，沟道，源极和漏极形成薄膜晶体管。 在图案化的光致抗蚀剂层，栅极绝缘层和薄膜晶体管上形成钝化层。 然后，去除图案化的光致抗蚀剂层，使得其上的钝化层被同时去除以形成图案化的钝化层，并且漏极被暴露。 在图案化的钝化层和漏极上形成像素电极。