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    Multi-level run-length limited finite state machine for magnetic recording channel
    51.
    发明授权
    Multi-level run-length limited finite state machine for magnetic recording channel 有权
    用于磁记录通道的多级游程限制有限状态机

    公开(公告)号：US08854755B2

    公开(公告)日：2014-10-07

    申请号：US13654893

    申请日：2012-10-18

    Applicant: LSI Corporation

    Inventor： Wu Chang ,  Razmik Karabed ,  Shaohua Yang ,  Fan Zhang

    IPC: G11B20/10 ,  G11B5/00 ,  G06F11/16 ,  G11B5/02

    CPC classification number: G11B5/02 ,  G06F11/16 ,  G11B20/10277

    Abstract: A system is described for constructing maximum transition run modulation code based upon a multi-level run-length limited finite state machine. A processor is configured to receive information from a hard disk drive via a read channel and recover data from the hard disk drive using maximum transition run modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct a maximum transition run modulation code to mimic the optimized Markov source based upon a finite state machine having a limited transition run length and a multi-level periodic structure.

    Abstract translation: 描述了一种基于多级游程限制有限状态机来构建最大过渡运行调制码的系统。 处理器被配置为经由读取通道从硬盘驱动器接收信息，并使用最大过渡运行调制码从硬盘驱动器恢复数据。 存储器具有被配置为由处理器执行以将磁记录通道建模为部分响应通道的计算机可执行指令，将信息源建模到磁记录通道以提供优化马尔可夫源，并且构建最大过渡运行调制码 基于具有有限转换行程长度和多级周期性结构的有限状态机模拟优化的马尔可夫源。

    Systems and methods for data processing control
    54.
    发明授权
    Systems and methods for data processing control 有权
    用于数据处理控制的系统和方法

    公开(公告)号：US08817404B1

    公开(公告)日：2014-08-26

    申请号：US13945787

    申请日：2013-07-18

    Applicant: LSI Corporation

    Inventor： Shu Li ,  Jun Xiao ,  Fan Zhang

    IPC: G11B5/09

    CPC classification number: G11B5/09 ,  G11B20/10268

    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for improving performance and/or resource utilization based upon channel characteristics.

    Abstract translation: 本发明涉及用于数据处理的系统和方法，更具体地涉及用于基于信道特性改进性能和/或资源利用的系统和方法。

    Low Density Parity Check Decoder With Miscorrection Handling
    56.
    发明申请
    Low Density Parity Check Decoder With Miscorrection Handling 有权
    低密度奇偶校验解码器与误码处理

    公开(公告)号：US20140164866A1

    公开(公告)日：2014-06-12

    申请号：US13708941

    申请日：2012-12-08

    Applicant: LSI CORPORATION

    Inventor： Anatoli A. Bolotov ,  Shaohua Yang ,  Zongwang Li ,  Mikhail I. Grinchuk ,  Lav D. Ivanovic ,  Fan Zhang ,  Yang Han

    IPC: H03M13/13

    CPC classification number: H03M13/13 ,  H03M13/1111 ,  H03M13/1142

    Abstract: A data processing system is disclosed including a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected.

    Abstract translation: 公开了一种数据处理系统，包括解码器电路，校正子计算电路和散列计算电路。 解码器电路可操作以基于复合矩阵的第一部分将解码算法应用于解码器输入以产生码字。 校正子计算电路可操作以基于码字和复合矩阵的第一部分来计算校正子。 散列计算电路可操作以基于复合矩阵的第二部分来计算散列。 当校验子指示基于复合矩阵的第一部分的码字是正确的但是第二测试指示码字被修正时，解码器电路还可操作以校正散列上的码字。

    PATTERN-DEPENDENT SHORT MEDIA DEFECT DETECTION
    60.
    发明申请
    PATTERN-DEPENDENT SHORT MEDIA DEFECT DETECTION 有权
    模式相关短缺媒体缺陷检测

    公开(公告)号：US20140095963A1

    公开(公告)日：2014-04-03

    申请号：US13631075

    申请日：2012-09-28

    Applicant: LSI CORPORATION

    Inventor： Fan Zhang ,  Wu Chang

    IPC: G06F11/00 ,  G06F7/04

    CPC classification number: G06F11/00 ,  H03M13/1102 ,  H03M13/3723 ,  H03M13/6337 ,  H04L1/005

    Abstract: Systems and methods for computing sign disagreement between Le and La signals may implement one or more operations including, but not limited to: receiving an extrinsic log likelihood ratio (LLR) value; incrementing a sign-disagreement counter according to a sign disagreement between the extrinsic LLR value and an a priori LLR value; providing a value of the sign-disagreement counter to a binary short media defect (SMD) detector.

    Abstract translation: 用于计算Le和La信号之间符号不一致的系统和方法可以实现一个或多个操作，包括但不限于：接收外在对数似然比（LLR）值; 根据外在LLR值和先验LLR值之间的符号不一致，增加符号不一致计数器; 提供二进制短介质缺陷（SMD）检测器的符号分歧计数器的值。

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