公开(公告)号：US20060108662A1

公开(公告)日：2006-05-25

申请号：US10904681

申请日：2004-11-23

申请人： Chandrasekharan Kothandaraman ,  Edward Maciejewski

发明人： Chandrasekharan Kothandaraman ,  Edward Maciejewski

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is preferably a material that minimizes stresses on the crystalline body, such as an oxide. The body may be doped, and may also include a silicide layer on the upper surface. This fuse structure may be successfully programmed over a wide range of programming voltages and time.

摘要翻译： 描述了一种熔丝结构及其形成方法，其中熔丝的主体由绝缘体上的结晶半导体本体形成，绝缘体优选由绝缘体上硅晶片，被填充电介质环绕。 填充电介质优选是使结晶体（例如氧化物）上的应力最小化的材料。 主体可以被掺杂，并且还可以在上表面上包括硅化物层。 这种熔丝结构可以在广泛的编程电压和时间范围内成功编程。

公开(公告)号：US20050167728A1

公开(公告)日：2005-08-04

申请号：US10769101

申请日：2004-01-29

申请人： Chandrasekharan Kothandaraman ,  Danny Shum

发明人： Chandrasekharan Kothandaraman ,  Danny Shum

IPC分类号： G11C16/04 ,  G11C29/00 ,  H01L21/336 ,  H01L23/525 ,  H01L27/115 ,  H01L29/788 ,  H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C29/789 ,  G11C2216/10 ,  H01L23/5256 ,  H01L29/66825 ,  H01L29/7885 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically programmable transistor fuse having a double-gate arrangement disposed in a single layer of polysilicon in which a first gate is disposed overlapping a portion of a source region and a second gate is insulated from the first gate and disposed overlapping a portion of a drain region. The first gate includes a terminal for receiving an externally applied control signal and the second gate is capacitively couple to the drain region in which a coupling device is included for increasing the capacitive coupling of the second gate and the drain region for enabling reduction in fuse programming voltage.

摘要翻译： 具有设置在单层多晶硅中的双栅极布置的电可编程晶体管熔丝，其中第一栅极被布置成与源极区域的一部分重叠并且第二栅极与第一栅极绝缘，并且与漏极的一部分重叠 地区。 第一栅极包括用于接收外部施加的控制信号的端子，并且第二栅极电容耦合到其中包括耦合装置的漏极区域，以增加第二栅极和漏极区域的电容耦合，以便能够减少熔丝编程 电压。

公开(公告)号：US06828652B2

公开(公告)日：2004-12-07

申请号：US10140592

申请日：2002-05-07

申请人： Chandrasekharan Kothandaraman

发明人： Chandrasekharan Kothandaraman

IPC分类号： H01L2900

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse structure (30) formed in a semiconductor device is provided. The fuse structure (30) includes a layer of fuse material (32), a first contact (40), and a second contact (42). The first contact (40) has a first edge (54). At least a portion of the first edge (54) abuts the fuse material layer (32). The second contact (42) has a second edge (55). At least a portion of the second edge (55) abuts the fuse material layer (32). The first edge (54) faces the second edge (55). The first edge (54) is separated from the second edge (55) by a spaced distance (58). A conductive portion of the fuse material layer (32) electrically connects between the first edge (54) and the second edge (55) within the spaced distance (58). The abutting portion of the first edge (54) has a first length. The abutting portion of the second edge (55) has a second length. The first length is greater than the second length.

摘要翻译： 提供形成在半导体器件中的熔丝结构（30）。 熔丝结构（30）包括一层熔丝材料（32），一个第一触点（40）和一个第二触点（42）。 第一触点（40）具有第一边缘（54）。 第一边缘（54）的至少一部分邻接熔丝材料层（32）。 第二触点（42）具有第二边缘（55）。 第二边缘（55）的至少一部分邻接熔丝材料层（32）。 第一边缘（54）面向第二边缘（55）。 第一边缘（54）与第二边缘（55）分开一段距离（58）。 熔丝材料层（32）的导电部分在间隔距离（58）内在第一边缘（54）和第二边缘（55）之间电连接。 第一边缘（54）的邻接部分具有第一长度。 第二边缘（55）的邻接部分具有第二长度。 第一长度大于第二长度。

公开(公告)号：US06432760B1

公开(公告)日：2002-08-13

申请号：US09751475

申请日：2000-12-28

申请人： Chandrasekharan Kothandaraman ,  Michael Stetter ,  Sundar K. Iyer

发明人： Chandrasekharan Kothandaraman ,  Michael Stetter ,  Sundar K. Iyer

IPC分类号： H01L218238

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved fuse structure in an integrated circuit (IC) structure is made by forming a gate stack comprised of layers of polysilicon and a silicide. Subsequent to the formation of the silicide layer, an etch stop silicon nitride layer is deposited over the silicide layer. The silicon nitride layer is patterned to expose the silicide layer. A soft passivation layer is deposited over the exposed silicide layer. The soft passivation layer has a low thermal conductivity which confines energy in the silicide layer, minimizing the current needed to program the fuse. The inherent ductility of the soft passivation layer prevents the generation of cracks in the surrounding layers.

摘要翻译： 通过形成由多晶硅层和硅化物层构成的栅极堆叠来形成集成电路（IC）结构中的改进的熔丝结构。 在形成硅化物层之后，在硅化物层上沉积蚀刻停止氮化硅层。 图案化氮化硅层以暴露硅化物层。 在钝化的硅化物层上沉积软钝化层。 软钝化层具有低热导率，其将能量限制在硅化物层中，使得对熔丝编程所需的电流最小化。 软钝化层的固有延展性防止周围层产生裂纹。

公开(公告)号：US09184129B2

公开(公告)日：2015-11-10

申请号：US13004129

申请日：2011-01-11

申请人： Byeongju Park ,  Subramanian S. Iyer ,  Chandrasekharan Kothandaraman

发明人： Byeongju Park ,  Subramanian S. Iyer ,  Chandrasekharan Kothandaraman

IPC分类号： H01L23/525 ,  H01L27/112 ,  G11C17/16

CPC分类号： H01L23/5252 ,  G11C17/165 ,  G11C2229/763 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/928 ,  H01L2924/00

摘要： The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.

摘要翻译： 本发明提供了具有集成加热元件的反熔丝结构及其编程方法，反熔丝结构包括第一和第二导体以及形成在导体之间的介电层，其中一个或两个导体用作传统的反熔丝导体和 作为用于在编程期间直接加热反熔丝介电层的加热元件。

公开(公告)号：US20140033330A1

公开(公告)日：2014-01-30

申请号：US13561185

申请日：2012-07-30

申请人： Daniel Jacob Fainstein ,  Chandrasekharan Kothandaraman

发明人： Daniel Jacob Fainstein ,  Chandrasekharan Kothandaraman

IPC分类号： H03K5/24 ,  G06F21/00

CPC分类号： G06F21/73 ,  G06F7/588 ,  G06F21/00 ,  G06F21/30 ,  G06F2221/2129 ,  H02H3/24 ,  H04L9/3278

摘要： Methods and circuits for undiscoverable physical chip identification are disclosed. Embodiments of the present invention provide an intrinsic bit element that comprises two transistors. The two transistors form a pair in which one transistor has a wide variability in threshold voltage and the other transistor has a narrow variability in threshold voltage. The wide variability is achieved by making a transistor with a smaller width and length than the other transistor in the pair. The variation of the threshold voltage of the wide variability transistor means that in the case of copies of intrinsic bit elements being made, some of the “copied” wide variability transistors will have significantly different threshold voltages, causing some of the intrinsic bit elements of a copied chip to read differently than in the original chip from which they were copied.

摘要翻译： 公开了用于不可发现的物理芯片识别的方法和电路。 本发明的实施例提供了包括两个晶体管的本征位元件。 两个晶体管形成一对，其中一个晶体管具有很大的阈值电压变化，另一个晶体管的阈值电压变化很小。 通过制造具有比该对中的另一个晶体管更小的宽度和长度的晶体管来实现广泛的变化。 宽变化率晶体管的阈值电压的变化意味着在内部位元素复制的情况下，一些“复制的”宽变化性晶体管将具有明显不同的阈值电压，导致一些固有位元素 复制芯片的读取方式与原始芯片的复制方式不同。

公开(公告)号：US08629049B2

公开(公告)日：2014-01-14

申请号：US13420724

申请日：2012-03-15

申请人： Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

发明人： Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

IPC分类号： H01L21/44

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fabrication method for fabricating an electrically programmable fuse method includes depositing a polysilicon layer on a substrate, patterning an anode contact region, a cathode contact region and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, depositing a silicide layer on the polysilicon layer, and forming a plurality of anisometric contacts on the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.

摘要翻译： 制造电可编程熔丝法的制造方法包括在衬底上沉积多晶硅层，图案化阳极接触区域，阴极接触区域和将阴极接触区域与阳极接触区域导电连接的熔断体，其可通过应用 编程电流，在多晶硅层上沉积硅化物层，以及在预定构型中分别在阴极接触区域和阳极接触区域的硅化物层上形成多个不规则接触。

公开(公告)号：US08525263B2

公开(公告)日：2013-09-03

申请号：US12355954

申请日：2009-01-19

申请人： Roger A. Booth ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

发明人： Roger A. Booth ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L21/28282 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/1052 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

摘要： A method of fabricating a memory device is provided that may begin with forming a layered gate stack overlying a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode overlying a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.

摘要翻译： 提供了一种制造存储器件的方法，其可以开始形成覆盖在半导体衬底上的层叠栅极堆叠并且图案化停止在层状栅极堆叠的高k栅极电介质层上的金属电极层，以提供第一金属栅电极和 半导体衬底上的第二金属栅电极。 在下一个处理顺序中，在第一金属栅电极上形成至少一个间隔物，该第一金属栅电极覆盖高k栅极电介质层的一部分，其中暴露高k栅极电介质的剩余部分。 蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质和具有对准边缘的第二高k栅极电介质 到第二金属栅电极的侧壁。

公开(公告)号：US20130063202A1

公开(公告)日：2013-03-14

申请号：US13612938

申请日：2012-09-13

申请人： Yan Zun Li ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

发明人： Yan Zun Li ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

IPC分类号： H01L23/544 ,  H01H37/76

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.

摘要翻译： 反熔丝具有一个导电类型的第一和第二半导体区域和它们之间具有相反导电类型的第三半导体区域。 接触第一区域的导电区域在横向于栅极的长尺寸方向的第二方向上具有长尺寸。 反熔丝阳极在第二方向上与第一区域间隔开，并且触点与第二区域连接。 在阳极和接触之间施加编程电压，栅极偏压足以完全导通反熔丝的场效应晶体管操作加热第一区域以向外驱动掺杂剂，导致第一区域的边缘更接近于 并且将第一和第二区域之间的电阻降低一个或多个数量级。

公开(公告)号：US08278155B2

公开(公告)日：2012-10-02

申请号：US13100456

申请日：2011-05-04

申请人： Geoffrey W. Burr ,  Chandrasekharan Kothandaraman ,  Chung Hon Lam ,  Xiao Hu Liu ,  Stephen M. Rossnagel ,  Christy S. Tyberg ,  Robert L. Wisnieff

发明人： Geoffrey W. Burr ,  Chandrasekharan Kothandaraman ,  Chung Hon Lam ,  Xiao Hu Liu ,  Stephen M. Rossnagel ,  Christy S. Tyberg ,  Robert L. Wisnieff

IPC分类号： H01L21/82 ,  H01L21/326 ,  H01L21/479

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.

摘要翻译： 集成电路中的可逆熔丝结构通过实现具有短路相变材料的熔断电池获得，所述相变材料与能够使电流通过相变材料线（熔丝电池）的通孔和线结构相接触。 电流通过熔丝电池，以便通过将结晶状态的相变材料加热至熔点，从而将材料从较小电阻的材料转变为更电阻的材料，然后快速将材料淬火成非晶状态。 可逆编程通过使较低电流通过熔丝电池来实现，以将高电阻率无定形材料转换成较低电阻率的晶体材料。 集成适当的感测电路以读取存储在熔丝中的信息，其中所述感测电路用于启用或禁用电路。