公开(公告)号：US20210271618A1

公开(公告)日：2021-09-02

申请号：US17324172

申请日：2021-05-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam

IPC: G06F13/16 ,  G11C16/08 ,  G11C16/32 ,  G11C16/04

Abstract: A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The synchronous data stage is between a first wave pipeline data stage of the plurality of wave pipeline data stages and a second wave pipeline data stage of the plurality of wave pipeline data stages. The clock path corresponds to the plurality of wave pipeline data stages. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.

公开(公告)号：US11061836B2

公开(公告)日：2021-07-13

申请号：US16448188

申请日：2019-06-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam

IPC: G06F1/08 ,  G06F13/16 ,  G11C16/08 ,  G11C16/32 ,  G11C16/04

Abstract: A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage between a data input node and a data output node. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The clock path includes a plurality of clock stages corresponding to the plurality of wave pipeline data stages between an input clock node and a return clock node. Each clock stage has a delay configured to be equal to a delay of the corresponding wave pipeline data stage. The wave pipeline includes a second data latch to latch the data on the data output node in response to a return clock signal on the return clock node. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.

公开(公告)号：US20210110856A1

公开(公告)日：2021-04-15

申请号：US17247267

申请日：2020-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/04 ,  G11C7/10 ,  G11C8/18

Abstract: A system might include a first writing device and a second writing device. The first writing device might write first data to an array of memory cells in response to a first clock cycle of a clock signal. The write of the first data exceeds one clock cycle of the clock signal. The second writing device is in parallel with the first writing device. The second writing device might write second data to the array of memory cells in response to a second clock cycle of the clock signal. The second clock cycle follows the first clock cycle and the write of the second data exceeds one clock cycle of the clock signal.

公开(公告)号：US10972078B2

公开(公告)日：2021-04-06

申请号：US16920315

申请日：2020-07-02

Applicant: Micron Technology, Inc.

Inventor： Guan Wang ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

IPC: G06F1/10 ,  H03K3/017 ,  H04L25/06 ,  H03K5/156 ,  G11C7/22 ,  G11C29/02 ,  H04L7/00 ,  H04L25/02 ,  G06F1/04

Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

公开(公告)号：US10891993B2

公开(公告)日：2021-01-12

申请号：US16429209

申请日：2019-06-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/04 ,  G11C8/18 ,  G11C16/04

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

公开(公告)号：US10802721B2

公开(公告)日：2020-10-13

申请号：US16398646

申请日：2019-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G11C7/10 ,  G06F3/06 ,  G11C16/32 ,  G11C16/26 ,  G06F12/0802 ,  G11C7/22 ,  G06F12/02

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal; to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal; and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

公开(公告)号：US20190258400A1

公开(公告)日：2019-08-22

申请号：US16398646

申请日：2019-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/32 ,  G11C7/10 ,  G11C7/22 ,  G06F12/0802 ,  G06F12/02

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal; to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal; and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

公开(公告)号：US20190190501A1

公开(公告)日：2019-06-20

申请号：US16204841

申请日：2018-11-29

Applicant: Micron Technology, Inc.

Inventor： Guan Wang ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam

IPC: H03K3/017 ,  G06F1/10 ,  H04L25/06 ,  G11C7/22 ,  H03K5/156

Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.

公开(公告)号：US09460803B1

公开(公告)日：2016-10-04

申请号：US14864990

申请日：2015-09-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Eric N. Lee ,  Ramin Ghodsi

IPC: G11C16/26 ,  G11C7/22 ,  G11C16/32 ,  G11C7/10 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C5/063 ,  G11C7/04 ,  G11C7/08 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/0483 ,  G11C16/32

Abstract: A system includes a plurality of sensing devices, a first multiplexer, a plurality of local return clock signal paths, a second multiplexer, and a data latch. Each sensing device outputs data onto a respective local data path in response to a clock signal on a clock signal path. The first multiplexor passes data from a selected local data path to a global data path. Each local return clock signal path is coupled to the clock signal path at a respective sensing device such that each local return clock signal path is routed along with a respective local data path. The second multiplexor passes a return clock signal from a selected local return clock signal path corresponding to the selected local data path to a global return clock signal path. The data latch latches the data on the global data path into the data latch in response to the return clock signal on the global return clock signal path.

Abstract translation: 系统包括多个感测装置，第一多路复用器，多个本地返回时钟信号路径，第二多路复用器和数据锁存器。 每个感测装置响应于时钟信号路径上的时钟信号将数据输出到相应的本地数据路径上。 第一多路复用器将数据从选定的本地数据路径传递到全局数据路径。 每个本地返回时钟信号路径在相应感测装置处耦合到时钟信号路径，使得每个本地返回时钟信号路径与相应的本地数据路径一起路由。 第二多路复用器将来自对应于所选择的本地数据路径的选择的本地返回时钟信号路径的返回时钟信号传递到全局返回时钟信号路径。 响应于全局返回时钟信号路径上的返回时钟信号，数据锁存器将全局数据通路上的数据锁存到数据锁存器中。

公开(公告)号：US09190133B2

公开(公告)日：2015-11-17

申请号：US13793347

申请日：2013-03-11

Applicant: Micron Technology, Inc.

Inventor： Dean K. Nobunaga ,  Ali Feiz Zarrin Ghalam ,  Xiaojiang Guo ,  Eric N. Lee

IPC: G06F12/00 ,  G11C11/00 ,  G06F12/08

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0683 ,  G06F12/0802 ,  G06F12/0893 ,  G06F13/1684 ,  G06F13/4068 ,  G06F2212/1016 ,  G06F2212/3042 ,  G11C5/066 ,  G11C7/1048 ,  G11C8/12 ,  G11C11/00

Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.

Abstract translation: 本文公开了用于减小数据总线上的电容的装置和方法。 根据一个或多个所描述的实施例，装置可以包括耦合到内部数据总线和命令和地址总线的多个存储器，每个存储器被配置为在命令和地址总线上接收命令。 多个存储器中的一个可以耦合到外部数据总线。 多个存储器中的一个可以被配置为当命令包括程序命令时向内部数据总线提供程序数据，并且多个存储器中的另一个是程序命令的目标存储器，并且可以被配置为将读取数据提供给 当命令包括读取命令并且多个存储器中的另一个是读取命令的目标存储器时的外部数据总线。