公开(公告)号：US20240028252A1

公开(公告)日：2024-01-25

申请号：US17872426

申请日：2022-07-25

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Dung V. Nguyen ,  Dave Scott Ebsen ,  Tomoharu Tanaka ,  James Fitzpatrick ,  Huai-Yuan Tseng ,  Akira Goda ,  Eric N. Lee

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/064 ,  G06F3/0604 ,  G06F3/0679

Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.

公开(公告)号：US20230386533A1

公开(公告)日：2023-11-30

申请号：US18232949

申请日：2023-08-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric N. Lee ,  Kishore Kumar Muchherla ,  Jeffrey S. McNeil ,  Jung-Sheng Hoei

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/14

CPC classification number: G11C7/106 ,  G11C7/1057 ,  G11C7/222 ,  G11C7/1087 ,  G11C7/14 ,  G11C7/1084

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.

公开(公告)号：US20230253052A1

公开(公告)日：2023-08-10

申请号：US18104201

申请日：2023-01-31

Applicant: Micron Technology, Inc.

Inventor： Tomoko Ogura Iwasaki ,  Eric N. Lee ,  June Lee

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/0433

Abstract: Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.

公开(公告)号：US20230214139A1

公开(公告)日：2023-07-06

申请号：US17858778

申请日：2022-07-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sundararajan Sankaranarayanan ,  Eric N. Lee

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0656 ,  G06F3/0679

Abstract: A second read command to read second data from an array of memory cells is detected. An initial voltage to be applied to at least one wordline coupled to at least a subset of the array of memory cells is caused prior to releasing a first data associated with a first read command stored in a page buffer. The initial voltage to increase to a target value is caused. The page buffer to sense the second data from a bitline coupled to a page of the subset of the array of memory cells is caused. The sensed second data out of the bitline into the page buffer is read responsive to determining that the first data has been released from the page buffer.

公开(公告)号：US11636904B2

公开(公告)日：2023-04-25

申请号：US17229476

申请日：2021-04-13

Applicant: Micron Technology, Inc.

Inventor： Yoav Weinberg ,  Eric N. Lee

IPC: G11C11/40 ,  G11C16/34 ,  G11C16/20 ,  G11C7/10 ,  G11C16/32 ,  G11C16/26

Abstract: A method includes determining, via status polling at a first interval, an indicator of an almost ready status of a set of memory cells of a memory device, based on the indicator of the almost ready status, determining the set of memory cells of the memory device is almost ready to complete execution of an operation on the set of memory cells of the memory device, and responsive to determining the set of memory cells of the memory device is almost ready to complete execution of the operation, performing status polling at a second interval.

公开(公告)号：US20230070445A1

公开(公告)日：2023-03-09

申请号：US17984916

申请日：2022-11-10

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Robert W. Strong ,  William Akin ,  Jeremy Binfet

IPC: G11C16/04 ,  G11C16/30 ,  G11C16/22 ,  G11C16/24 ,  G11C16/34

Abstract: A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.

公开(公告)号：US20230062226A1

公开(公告)日：2023-03-02

申请号：US17458795

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Robert W. Strong ,  William Akin ,  Jeremy Binfet

IPC: G11C16/16 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: A method includes receiving signaling indicative of performance of a sanitization operation to a processing device coupled to a memory device and applying a sanitization voltage to a plurality of memory blocks of the memory device. The sanitization voltage can be greater than an erase voltage of the plurality of memory blocks.

公开(公告)号：US20230018681A1

公开(公告)日：2023-01-19

申请号：US17951754

申请日：2022-09-23

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Dheeraj Srinivasan

IPC: G11C16/34 ,  G11C16/26 ,  G11C7/10 ,  G11C16/10

Abstract: A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.

公开(公告)号：US11456039B2

公开(公告)日：2022-09-27

申请号：US17102876

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Dheeraj Srinivasan

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C7/10

Abstract: A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.

公开(公告)号：US11367473B2

公开(公告)日：2022-06-21

申请号：US17247267

申请日：2020-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/04 ,  G11C7/10 ,  G11C8/18 ,  G11C16/04

Abstract: A system might include a first writing device and a second writing device. The first writing device might write first data to an array of memory cells in response to a first clock cycle of a clock signal. The write of the first data exceeds one clock cycle of the clock signal. The second writing device is in parallel with the first writing device. The second writing device might write second data to the array of memory cells in response to a second clock cycle of the clock signal. The second clock cycle follows the first clock cycle and the write of the second data exceeds one clock cycle of the clock signal.