公开(公告)号：US11545209B2

公开(公告)日：2023-01-03

申请号：US17333203

申请日：2021-05-28

Applicant: Micron Technology, Inc.

Inventor： Parthasarathy Gajapathy ,  Kallol Mazumder

IPC: G11C11/4076 ,  G06F1/3234 ,  G06F1/3296 ,  G11C11/4093

Abstract: Systems and methods for injecting a toggling signal in a command pipeline configured to receive a multiple command types for the memory device. Toggling circuitry is configured to inject the toggling signal into at least a portion of the command pipeline when the memory device is in a power saving mode and the command pipeline is clear of valid commands. The toggling is blocked from causing writes by disabling a data strobe when a command that is invalid in the power saving mode is asserted during the power saving mode.

公开(公告)号：US11003240B2

公开(公告)日：2021-05-11

申请号：US16684183

申请日：2019-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Parthasarathy Gajapathy

IPC: G11C11/408 ,  G06F3/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G06F13/16 ,  G11C11/4063

Abstract: The systems and methods provided herein relate to a command interface/memory device that supports multiple modes of command acquisition. A current command acquisition mode from a set of supported command acquisition modes that each define a corresponding command execution frequency is identified. Based upon the identified mode, clock cycles that will be used to acquire portions of a command address from are identified. The portions of the command address are acquired from the identified clock cycles and a command based upon the acquired portions of the command address is executed.

公开(公告)号：US10727840B2

公开(公告)日：2020-07-28

申请号：US16392474

申请日：2019-04-23

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder

IPC: H03L7/08 ,  H03L7/081 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

Abstract: Memory systems can include shifting an ODT information signal prior to passing it through a cloned DLL delay line. The shifted ODT information passes through a cloned DLL delay line to move it into a DLL domain. Meanwhile, a clock gate can use a command indication to select whether to provide a clock signal to a DLL delay line. The clock gate can block the clock signal in the absence of a read or write operation and can pass the clock signal during read or write operations. When the DLL delay line receives the clock signal, it delays the clock signal to be in the DLL domain. By locating the ODT shifter before the cloned DLL delay line, as opposed to after it, the ODT shifter doesn't need a signal passed through the DLL delay line. Preventing the clock signal from passing through the DLL delay line reduces power consumption.

公开(公告)号：US10699757B2

公开(公告)日：2020-06-30

申请号：US16428741

申请日：2019-05-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder

IPC: G11C7/10 ,  G11C11/4063 ,  H03K19/003 ,  H03K19/0175 ,  G11C7/22 ,  G11C29/02 ,  G11C29/50 ,  G11C11/4076 ,  G11C11/4093

Abstract: Devices, systems, and methods include controls for on-die termination (ODT) and data strobe signals. For example, a command to de-assert ODT for a data pin (DQ) during the read operation. An input, such as a mode register, receives an indication of a shift mode register value that corresponds to a number of shifts of a rising edge of the command in a backward or a falling edge in a forward direction. A delay chain delays the appropriate edge of received command the number of shifts in the corresponding direction to generate a shifted edge command signal. Combination circuitry then combines a falling edge command signal with a shifted rising edge command signal to form a transformed command.

公开(公告)号：US10481676B2

公开(公告)日：2019-11-19

申请号：US16205356

申请日：2018-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Parthasarathy Gajapathy

IPC: G11C7/10 ,  G06F3/00 ,  G06F13/16 ,  G11C11/4063

Abstract: The systems and methods provided herein acquire a command over multiple clock cycles and fires it. When a chip select signal (CS) transitions, a first portion of a command address is captured in a first clock cycle after the CS transitions. Then, a second portion of the command address is captured in a second clock cycle immediately after the first clock cycle or in a third clock cycle immediately following the second clock cycle. An internal command is fired, using the first portion of the command address and the second portion of the command address.

公开(公告)号：US10367512B1

公开(公告)日：2019-07-30

申请号：US15965663

申请日：2018-04-27

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder

IPC: H03L7/08 ,  H03L7/081 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

Abstract: Memory systems can include shifting an ODT information signal prior to passing it through a cloned DLL delay line. The shifted ODT information passes through a cloned DLL delay line to move it into a DLL domain. Meanwhile, a clock gate can use a command indication to select whether to provide a clock signal to a DLL delay line. The clock gate can block the clock signal in the absence of a read or write operation and can pass the clock signal during read or write operations. When the DLL delay line receives the clock signal, it delays the clock signal to be in the DLL domain. By locating the ODT shifter before the cloned DLL delay line, as opposed to after it, the ODT shifter doesn't need a signal passed through the DLL delay line. Preventing the clock signal from passing through the DLL delay line reduces power consumption.

公开(公告)号：US10270445B2

公开(公告)日：2019-04-23

申请号：US16013813

申请日：2018-06-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder

IPC: H03K21/00 ,  H03K19/0175 ,  G11C11/4076 ,  H03K3/037 ,  G11C7/10 ,  G11C7/22

Abstract: A semiconductor device includes a clock divider that receives a clock signal and generates even and odd clock signals. The clock signal includes a first frequency, while the even and odd clock signals each includes a second frequency that is half the first frequency. The semiconductor device also includes even and odd command paths coupled to the clock divider each having a set of logic and a set of flip-flops. The even command path receives a command and the even clock signal and outputs an even output signal. The odd command path receives the command and the odd clock signal and outputs an odd output signal. The semiconductor device also includes combination circuitry coupled to the even and odd command paths that combines the even and odd output signals.

公开(公告)号：US10249355B2

公开(公告)日：2019-04-02

申请号：US15203665

申请日：2016-07-06

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  G11C8/10

Abstract: Apparatuses and methods for providing active and inactive clock signals to a command path circuit are described. An example method includes providing an active clock signal to a command path for a first portion of a command cycle for a command of back-to-back commands. The command path decodes the command and provides an output command signal responsive to the clock signal. The method further includes providing an inactive clock signal to the command path for a second portion of the command cycle for the command of the back-to-back commands.

公开(公告)号：US20190096451A1

公开(公告)日：2019-03-28

申请号：US16200443

申请日：2018-11-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder

IPC: G11C7/10 ,  G11C7/22 ,  G11C29/02 ,  H03K19/0175 ,  H03K19/003 ,  G11C11/4063

CPC classification number: G11C7/1057 ,  G11C7/1045 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4063 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/022 ,  G11C29/50012 ,  H03K19/003 ,  H03K19/017509

Abstract: Devices, systems, and methods include controls for on-die termination (ODT) and data strobe signals. For example, a command to de-assert ODT for a data pin (DQ) during the read operation. An input, such as a mode register, receives an indication of a shift mode register value that corresponds to a number of shifts of a rising edge of the command in a backward or a falling edge in a forward direction. A delay chain delays the appropriate edge of received command the number of shifts in the corresponding direction to generate a shifted edge command signal. Combination circuitry then combines a falling edge command signal with a shifted rising edge command signal to form a transformed command.

公开(公告)号：US10162406B1

公开(公告)日：2018-12-25

申请号：US15692852

申请日：2017-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Parthasarathy Gajapathy

IPC: G11C11/4076 ,  G06F3/00 ,  G11C7/10 ,  G06F13/16 ,  G11C11/4063

Abstract: The systems and methods provided herein identify a command acquisition mode from a plurality of command acquisition modes of a command interface of a memory device. A state of a chip select signal (CS) is identified. When the CS transitions to low from high, a first portion of a command address is captured in a first clock cycle after the CS transitions. When the command acquisition mode is in a first mode, a second portion of the command address is captured in a second clock cycle immediately after the first clock cycle. Otherwise, when the command acquisition mode is in a second mode, the second portion of the command address is captured in a third clock cycle immediately following the second clock signal. An internal command is fired, using the first portion of the command address and the second portion of the command address.