公开(公告)号：US20230342048A1

公开(公告)日：2023-10-26

申请号：US17660195

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Mark Kalei Hadrick ,  Yu-Sheng Hsu ,  John Christopher Sancon ,  Kang-Yong Kim ,  Yang Lu

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: Described apparatuses and methods relate to self-refresh arbitration. In a memory system with multiple memory components, an arbiter is configured to manage the occurrence of self-refresh operations. In aspects, the arbiter can receive one or more self-refresh request signals from at least one memory controller for authorization to command one or more memory components to enter a self-refresh mode. Upon receiving the one or more self-refresh request signals, the arbiter, based on a predetermined configuration, can transmit one or more self-refresh enable signals to the at least one memory controller with authorization to command the one or more memory components to enter the self-refresh mode. The configuration can ensure that fewer than all memory components simultaneously enter the self-refresh mode. In so doing, memory components can perform self-refresh operations without exceeding an instantaneous power threshold. The arbiter can be included in, for instance, a Compute Express Link™ (CXL™) memory module.

公开(公告)号：US20230342047A1

公开(公告)日：2023-10-26

申请号：US17660192

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Mark Kalei Hadrick ,  Yu-Sheng Hsu ,  John Christopher Sancon ,  Kang-Yong Kim ,  Yang Lu

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: Described apparatuses and methods relate to self-refresh arbitration. In a memory system with multiple memory components, an arbiter is configured to manage the occurrence of self-refresh operations. In aspects, the arbiter can receive one or more self-refresh request signals from at least one memory controller for authorization to command one or more memory components to enter a self-refresh mode. Upon receiving the one or more self-refresh request signals, the arbiter, based on a predetermined configuration, can transmit one or more self-refresh enable signals to the at least one memory controller with authorization to command the one or more memory components to enter the self-refresh mode. The configuration can ensure that fewer than all memory components simultaneously enter the self-refresh mode. In so doing, memory components can perform self-refresh operations without exceeding an instantaneous power threshold. The arbiter can be included in, for instance, a Compute Express Link™ (CXL™) memory module.

公开(公告)号：US20230121992A1

公开(公告)日：2023-04-20

申请号：US17502792

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyunyoo Lee

IPC: G11C7/10

Abstract: Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. The external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.

公开(公告)号：US11621031B2

公开(公告)日：2023-04-04

申请号：US17302206

申请日：2021-04-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim ,  Sourabh Dhir ,  Keun Soo Song

IPC: G11C5/14 ,  G11C11/4074

Abstract: In some examples, memory die may include a selection pad, which may be coupled to a power potential. The selection pad may provide a signal to a selection control circuit, which may control a selection circuit to couple a power pad to one of multiple power rails. In some examples, a power management integrated circuit may include a selection circuit to provide one power potential to a package including a memory die when a selection signal has a logic level and another power potential when the selection signal has another logic level.

公开(公告)号：US20230100397A1

公开(公告)日：2023-03-30

申请号：US17959730

申请日：2022-10-04

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Saira S. Malik ,  Hyunyoo Lee ,  Kang-Yong Kim

IPC: G11C11/4074 ,  H01L25/065 ,  H02M3/156 ,  H01L27/108

Abstract: Methods, systems, and devices for die voltage regulation are described. A device may include a first die and second die. A component that generates voltage on the first die may be connected to a capacitor on the second die through a conductive line. The conductive line may allow the capacitor on the second die to regulate voltage generated by the component on the first die.

公开(公告)号：US20230038894A1

公开(公告)日：2023-02-09

申请号：US17875960

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim

IPC: G11C7/10 ,  G11C29/46

Abstract: Methods, systems, and devices for selective access for grouped memory dies are described. A memory device may be configured with a select die access protocol for a group of memory dies that share a same channel. The protocol may be enabled by one or more commands from the host device, which may be communicated to each of the memory dies of the group via the channel. The command(s) may indicate a first set of one or more memory dies of the group for which a set of commands may be enabled and may also indicate a second set of one or more memory dies of the group for which at least a subset of the set of commands is disabled. When the select die access mode is enabled, the disabled memory dies may be restricted from performing the subset of commands received via the channel.

公开(公告)号：US11550741B2

公开(公告)日：2023-01-10

申请号：US17167475

申请日：2021-02-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G06F9/30 ,  G11C7/22 ,  G11C29/02 ,  G11C16/32 ,  G06F12/02 ,  G11C16/08

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US20220406357A1

公开(公告)日：2022-12-22

申请号：US17804414

申请日：2022-05-27

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Keun Soo Song

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: This document describes apparatuses and techniques for multi-rail power transition. In various aspects, a power rail controller transitions a memory circuit (e.g., of a memory die) from a first power rail to a second power rail. The power rail controller then changes a voltage of the first power rail from a first voltage to a second voltage. The power rail controller may also adjust termination impedance or a clock frequency of the memory circuit before transitioning the memory circuit to the second power rail. The power rail controller then transitions the memory circuit from the second power rail to the first power rail to enable operation of the memory circuit at the second voltage. By so doing, the power rail controller may improve the reliability of memory operations when transitioning operation of the memory circuit from the first voltage to the second voltage.

公开(公告)号：US20220406344A1

公开(公告)日：2022-12-22

申请号：US17648403

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Hyunyoo Lee ,  Kang-Yong Kim ,  Taeksang Song

IPC: G11C7/10 ,  G11C8/06 ,  G11C11/4074

Abstract: Methods, systems, and devices for programmable column access are described. A device may transfer voltages from memory cells of a row in a memory array to respective digit lines for the memory cells. The voltages may be indicative of logic values stored at the memory cells. The device may communicate respective control signals to a set of multiplexers coupled with the digit lines, where each multiplexer is coupled with a respective subset of the digit lines. Each multiplexer may couple a digit line of the respective subset of digit lines with a respective sense component for that multiplexer based on the respective control signal for that multiplexer.

公开(公告)号：US20220301604A1

公开(公告)日：2022-09-22

申请号：US17805270

申请日：2022-06-03

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim

IPC: G11C7/10 ,  G11C8/10 ,  G11C8/18

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.