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    Aggregated and Virtualized Solid State Drives Accessed via Multiple Logical Address Spaces
    51.
    发明申请
    Aggregated and Virtualized Solid State Drives Accessed via Multiple Logical Address Spaces 有权

    公开(公告)号：US20210157719A1

    公开(公告)日：2021-05-27

    申请号：US17170766

    申请日：2021-02-08

    Applicant: Micron Technology, Inc.

    Inventor： Christopher Joseph Bueb ,  Poorna Kale

    IPC: G06F12/02 ,  G06F3/06 ,  G06F13/38 ,  G06F12/10 ,  G06F13/40

    Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. The drive aggregator associates the host interfaces with different logical address spaces, interprets commands received from the host interfaces in the different logical address spaces, and implements the commands using the plurality of component solid state drives. Some of the host interfaces can be configured to share a common logical address space. Some of the logical address spaces can be configured to have an overlapping region that are hosted on the same set of memory units such that the memory units can be addressed in any of the logical address spaces having the overlapping region.

    BACKGROUND OPERATION SELECTION BASED ON HOST IDLE TIME
    52.
    发明申请
    BACKGROUND OPERATION SELECTION BASED ON HOST IDLE TIME 有权

    公开(公告)号：US20210141561A1

    公开(公告)日：2021-05-13

    申请号：US16678850

    申请日：2019-11-08

    Applicant: Micron Technology, Inc.

    Inventor： Poorna Kale ,  Ashok Sahoo

    IPC: G06F3/06

    Abstract: An indication can be received that a host system is to become idle for a period of time. A background operation can be selected from multiple background operations based on the period of time that the host system is to become idle. The selected background operation can be executed during the period of time that the host system is to become idle.

    MEMORY COMPONENT WITH A BUS TO TRANSMIT DATA FOR A MACHINE LEARNING OPERATION AND ANOTHER BUS TO TRANSMIT HOST DATA
    53.
    发明申请
    MEMORY COMPONENT WITH A BUS TO TRANSMIT DATA FOR A MACHINE LEARNING OPERATION AND ANOTHER BUS TO TRANSMIT HOST DATA 有权

    公开(公告)号：US20210110250A1

    公开(公告)日：2021-04-15

    申请号：US16601376

    申请日：2019-10-14

    Applicant: Micron Technology, Inc.

    Inventor： Poorna Kale ,  Amit Gattani

    IPC: G06N3/08 ,  G06F13/16 ,  G06N3/04

    Abstract: Memory cells can include a memory region to store a machine learning model and input data and another memory region to store host data from a host system. An in-memory logic can be coupled to the plurality of memory cells and can perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional host data from the host system and can provide the additional host data to the memory component for the other memory region of the plurality of memory cells. An additional bus can receive machine learning data from the host system and can provide the machine learning data to the memory component for the in-memory logic that is to perform the machine learning operation.

    Detailed failure notifications in memory sub-systems
    54.
    发明授权
    Detailed failure notifications in memory sub-systems 有权

    公开(公告)号：US10977139B1

    公开(公告)日：2021-04-13

    申请号：US16601028

    申请日：2019-10-14

    Applicant: Micron Technology, Inc.

    Inventor： Christopher J. Bueb ,  Poorna Kale

    IPC: G06F11/00 ,  G06F11/16 ,  G06F11/07 ,  G06F11/30 ,  G11C11/408 ,  G11C29/52 ,  G11C11/409 ,  G06F12/02

    Abstract: Disclosed is a system comprising a memory component and a processing device operatively coupled with the memory component, to provide, to a host system, geometric parameters of the memory component, receive, from the host system, a first data to be stored in the memory component, execute a first write operation to program the first data into the memory component, detect that the first write operation has failed, provide a failure notification to the host system, wherein the failure notification comprises an indication of a range of memory cells storing, after the first write operation, incorrect data, and receive, from the host system, a second data to be stored in the memory component, in response to the host system identifying, based on the geometric parameters and the failure notification, a range of logical addresses of the memory component corresponding to the range of memory cells storing incorrect data.

    PREDICTIVE MAINTENANCE OF AUTOMOTIVE BATTERY
    55.
    发明申请
    PREDICTIVE MAINTENANCE OF AUTOMOTIVE BATTERY 有权

    公开(公告)号：US20210049480A1

    公开(公告)日：2021-02-18

    申请号：US16538097

    申请日：2019-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Poorna Kale ,  Robert Richard Noel Bielby

    IPC: G06N5/04 ,  G06N3/04 ,  G06N3/08 ,  G10L25/51 ,  G10L25/30

    Abstract: Systems, methods and apparatus of predictive maintenance of automotive battery. For example, a vehicle has: an electric motor; battery configured to power at least the electric motor; one or more sensors configured to measure operating parameters of the battery; an artificial neural network configured to analyze the operating parameters of the battery as a function of time to generate a result; and at least one processor configured to generate a suggestion for a maintenance service of the battery based on the result from the artificial neural network analyzing the operating parameters of the battery. For example, the electric motor can be part of an engine starter for an internal combustion engine, or a motor for an electric vehicle.

    STORAGE AND ACCESS OF NEURAL NETWORK INPUTS IN AUTOMOTIVE PREDICTIVE MAINTENANCE
    56.
    发明申请
    STORAGE AND ACCESS OF NEURAL NETWORK INPUTS IN AUTOMOTIVE PREDICTIVE MAINTENANCE 有权

    公开(公告)号：US20210049479A1

    公开(公告)日：2021-02-18

    申请号：US16538073

    申请日：2019-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Poorna Kale ,  Robert Richard Noel Bielby

    IPC: G06N5/04 ,  G06N3/08 ,  G06F3/06 ,  G05B23/02

    Abstract: Systems, methods and apparatus of optimizing neural network computations of predictive maintenance of vehicles. For example, a data storage device of a vehicle includes: a host interface configured to receive a sensor data stream from at least one sensor configured on the vehicle; at least one storage media component having a non-volatile memory; and a controller. The non-volatile memory is configured into multiple partitions (e.g., namespaces) having different sets of memory operation settings configured for different types of data related to an artificial neural network (ANN). The partitions include an input partition configured to store input data to the ANN. The sensor data stream is applied in the ANN to predict a maintenance service of the vehicle. The memory units of the input partition can be configured for enhanced endurance, cyclic sequential overwrite of a continuous input stream.

    Deep learning access and authentication in a computing architecture
    60.
    发明授权
    Deep learning access and authentication in a computing architecture 有权

    公开(公告)号：US12299110B2

    公开(公告)日：2025-05-13

    申请号：US17808921

    申请日：2022-06-24

    Applicant: Micron Technology, Inc.

    Inventor： Poorna Kale

    IPC: G06F21/44 ,  G06N3/08

    Abstract: Methods, systems, and devices for deep learning access and authentication in a computing architecture are described. A computing system a processor, a deep learning device, and a memory system. The deep learning device may be operable to perform operations associated with the processor using a neural network. The memory system enable or disable access to the deep learning device by the processor. For example, the memory system may verify whether the processor is authorized to access the deep learning device and enable or disable access based on the verification. If access is enabled, the deep learning device may perform the one or more operations associated with the processor. If access is disabled, the deep learning device may be restricted from performing the one or more operations associated with the processor.

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