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    PERFORMING SELECT GATE INTEGRITY CHECKS TO IDENTIFY AND INVALIDATE DEFECTIVE BLOCKS
    56.
    发明公开
    PERFORMING SELECT GATE INTEGRITY CHECKS TO IDENTIFY AND INVALIDATE DEFECTIVE BLOCKS 审中-公开

    公开(公告)号：US20230187009A1

    公开(公告)日：2023-06-15

    申请号：US17550462

    申请日：2021-12-14

    Applicant: Micron Technology, Inc.

    Inventor： Zhongguang Xu ,  Zhenlei Shen ,  Murong Lang

    IPC: G06F3/06

    CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679

    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a parameter value of a select gate associated with a first set of memory cells; responsive to determining that the parameter value satisfies a threshold criterion, marking the first block in a grown bad block (GBB) data structure; performing one or more pulse operations on the first block to invalidate data stored on the block; receiving, from a host system, an enhanced erase command referencing a second block; and responsive to determining that the second block is marked in the GBB data structure, discarding the enhanced erase command.

    SELECTIVE DATA PATTERN WRITE SCRUB FOR A MEMORY SYSTEM
    57.
    发明申请
    SELECTIVE DATA PATTERN WRITE SCRUB FOR A MEMORY SYSTEM 有权

    公开(公告)号：US20230062652A1

    公开(公告)日：2023-03-02

    申请号：US17463207

    申请日：2021-08-31

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhongguang Xu ,  Murong Lang ,  Zhenming Zhou

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

    Abstract: A system includes a memory device having a plurality of memory cells and a processing device operatively coupled to the memory device. The processing device is to determine to perform a rewrite on at least a portion of the plurality of memory cells. The processing device can determine that a number of rewrite operations at first subset of memory cells storing a first logic state fail to satisfy a threshold criterion. The processing device can also cause a rewrite of data stored at a second subset of memory cells storing a second logic state in response to determining the number of rewrite operations performed at the first subset of memory cells fail to satisfy the threshold criterion.

    ADJUSTING READ-LEVEL THRESHOLDS BASED ON WRITE-TO-WRITE DELAY
    58.
    发明申请
    ADJUSTING READ-LEVEL THRESHOLDS BASED ON WRITE-TO-WRITE DELAY 有权

    公开(公告)号：US20230050305A1

    公开(公告)日：2023-02-16

    申请号：US17402279

    申请日：2021-08-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhongguang Xu ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

    IPC: G11C16/26 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34

    Abstract: A method includes performing a first write operation that writes data to a first memory unit of a group of memory units in a memory device, determining a write-to-write (W2W) delay based on a time difference between the first write operation and a second write operation on a memory unit in the group of memory units, wherein the second write operation occurred prior to the first write operation, identifying a threshold time criterion that is satisfied by the W2W delay, identifying a first read voltage level associated with the threshold time criterion, and associating the first read voltage level with a second memory unit of the group of memory units. The second memory unit can be associated with a second read voltage level that satisfies a selection criterion based on a comparison of the second read voltage level to the first read voltage level.

    DYNAMIC READ-LEVEL THRESHOLDS IN MEMORY SYSTEMS
    59.
    发明申请
    DYNAMIC READ-LEVEL THRESHOLDS IN MEMORY SYSTEMS 有权

    公开(公告)号：US20230043877A1

    公开(公告)日：2023-02-09

    申请号：US17396386

    申请日：2021-08-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhongguang Xu ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

    IPC: G06F3/06 ,  G11C16/26 ,  G11C16/32 ,  G01K13/00

    Abstract: A current operating characteristic value of a unit of the memory device is identified. An operating characteristic threshold value is identified from a set of operating characteristic thresholds, where the current operating characteristic value satisfies an operating characteristic threshold criterion that is based on the operating characteristic threshold value. A set of write-to-read (W2R) delay time thresholds that corresponds to the operating characteristic threshold value is identified from a plurality of sets of W2R delay time thresholds. Each of the W2R delay time thresholds in the set is associated with a corresponding read voltage level. A W2R delay time threshold associated with a W2R delay time threshold criterion is identified from the set of W2R delay time thresholds, where the W2R threshold criterion is satisfied by a current W2R delay time of the memory sub-system. A read voltage level associated with the identified W2R delay time threshold is identified.

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