Asynchronous PCM common decoding apparatus
    51.
    发明授权
    Asynchronous PCM common decoding apparatus 失效
    异步PCM通用解码设备

    公开(公告)号:US4099029A

    公开(公告)日:1978-07-04

    申请号:US760790

    申请日:1977-01-19

    IPC分类号: H04J3/02 H04J3/17 H04J6/02

    CPC分类号: H04J3/02 H04J3/17

    摘要: An asynchronous PCM common decoding apparatus decodes asynchronous PCM signals sent from a plurality of transmitter sources. The apparatus includes a plurality of receiver units each of which generate a digital signal to be decoded, a channel-number-designating signal, and a decode-requesting signal. One or more decoders are provided to decode the digital signals from the receiver units to analog signals. The decoders produce status signals indicating availabilities of the decoders for decoding the digital signals. A common control unit is responsive to both the decode-requesting signals and the status signals to successively allot a combination of a given receiver and a given decoder.

    Non-volatile semiconductor memory device

    公开(公告)号:US6011287A

    公开(公告)日:2000-01-04

    申请号:US31681

    申请日:1998-02-27

    申请人: Yasuo Itoh Koji Sakui

    发明人: Yasuo Itoh Koji Sakui

    CPC分类号: H01L27/115 G11C16/0483

    摘要: In a NAND EEPROM using the local self-boosting system, an intermediate voltage which allows a memory cell adjacent to a selected memory cell to be turned on is applied to the control gate of the adjacent memory cell. As a result, even if the adjacent memory cell is in a normally-off state, the potential of a bit line can be transmitted to the adjacent memory cell. Thus, the reliability of the write inhibition in a non-selected NAND memory cell column is improved, while data can be written at random into a plurality of memory cells in a selected NAND memory cell column. When data is to be erased, an absolute value of an erasing voltage applied to a control gate can be less. As a result, data can be erased by a lower erasure voltage than that required in the conventional art. Consequently, the element refinement, the reliability and the yield can be further improved.

    High voltage generator circuit
    53.
    发明授权
    High voltage generator circuit 失效
    高压发生器电路

    公开(公告)号:US5898335A

    公开(公告)日:1999-04-27

    申请号:US754795

    申请日:1996-11-21

    CPC分类号: G05F3/242 G11C5/145 H02M3/073

    摘要: A high voltage generator circuit comprises a boosting circuit, limiter circuit, and a bypass circuit. When a supply voltage is inputted into the boosting circuit, a high voltage is generated and supplied to the limiter circuit. When the high voltage generated by the boosting circuit exceeds a limit voltage of the limiter circuit, the limiter circuit operates and the output voltage of the boosting circuit is thus maintained at a constant value. When the output voltage exceeds the limit voltage of the limiter circuit and an output current of the boosting circuit exceeds a reference value, a portion of the output current of the boosting circuit equivalent to a difference between the output current and a predetermined value is bypassed and discharged by the bypass circuit stated above.

    摘要翻译: 高压发生器电路包括升压电路,限幅电路和旁路电路。 当电源电压输入到升压电路时,产生高电压并提供给限幅器电路。 当升压电路产生的高电压超过限制电路的限制电压时,限制电路工作,升压电路的输出电压因此维持在恒定值。 当输出电压超过限制电路的限制电压并且升压电路的输出电流超过参考值时,旁路与升压电路的输出电流的一部分相当于输出电流与预定值之间的差值, 由上述旁路电路放电。

    Semiconductor memory address lines with varied interval contact holes
    55.
    发明授权
    Semiconductor memory address lines with varied interval contact holes 失效
    具有不同间隔接触孔的半导体存储器地址线

    公开(公告)号:US4638458A

    公开(公告)日:1987-01-20

    申请号:US715360

    申请日:1985-03-25

    申请人: Yasuo Itoh

    发明人: Yasuo Itoh

    摘要: According to a memory of the invention which can read/write data, word lines are connected to memory cells arranged on a semiconductor substrate. Each word line has a double layered structure comprising first and second conductive lines. An insulative layer is sandwiched between the conductive lines. Since the insulative layer has a plurality of contact holes formed along the extended direction of the first and second lines and spaced by an irregular pitch, the stacked lines are discontinuously and electrically connected to each other through these contact holes.

    摘要翻译: 根据可读/写数据的本发明的存储器,字线连接到布置在半导体衬底上的存储单元。 每个字线具有包括第一和第二导线的双层结构。 绝缘层夹在导线之间。 由于绝缘层具有沿着第一和第二线的延伸方向形成并且间隔不规则间距的多个接触孔,所以堆叠的线通过这些接触孔不连续地电连接。

    Echo canceller and echo suppressor for frequency divisional attenuation
of acoustic echoes
    56.
    发明授权
    Echo canceller and echo suppressor for frequency divisional attenuation of acoustic echoes 失效
    回声消除器和回声抑制器,用于声学回波的分频衰减

    公开(公告)号:US4591670A

    公开(公告)日:1986-05-27

    申请号:US532628

    申请日:1983-09-15

    申请人: Yasuo Itoh

    发明人: Yasuo Itoh

    CPC分类号: H04B3/20

    摘要: An echo cancelling circuit is composed of digital circuits. An echo canceller is supplied with lower send-in and receive-in components derived from a send-in and a receive-in digital signal, respectively, in a lower frequency band below a predetermined frequency. The echo canceller produces a lower digital signal component which is free from a lower echo signal component. The echo canceller furthermore produces a control signal indicative of presence and absence of a lower voice signal component in the lower send-in component. Controlled by the control signal and supplied with a higher send-in component of a frequency band higher than the predetermined frequency, an adjustable attenuator produces a higher digital signal component in which a higher echo signal component is suppressed with no attenuation and either a constant or an adjustable positive attenuation given to the higher send-in component when the control signal indicates presence and absence of the lower voice signal component, respectively. The lower and the higher digital signal components are combined into a send-out signal exempted from the echo signal, which may or may not comprise a reverberation signal introduced into the send-in digital signal by audible sound reproduced from a voice signal carried by the receive-in digital signal.

    摘要翻译: 回波消除电路由数字电路组成。 在低于预定频率的较低频带中,回波消除器分别被提供有从发送和接收数字信号导出的较低的发送和接收分量。 回波消除器产生较低的数字信号分量,其没有较低的回波信号分量。 回波消除器进一步产生指示下部发送单元中存在和不存在较低语音信号分量的控制信号。 由控制信号控制并提供高于预定频率的频带的更高的发送分量,可调衰减器产生较高的数字信号分量,其中较高的回波信号分量被抑制而无衰减,或者是常数或 当控制信号分别指示存在和不存在较低语音信号分量时,给予较高发送分量的可调节的正衰减。 较低和较高的数字信号分量被组合成从回波信号中免除的发送信号,其可以或可以不包括通过从由所接收的语音信号携带的语音信号再现的可听声音引入到接收数字信号中的混响信号 接收数字信号。

    System for demodulating angle-modulated signals
    57.
    发明授权
    System for demodulating angle-modulated signals 失效
    用于解调角度调制信号的系统

    公开(公告)号:US4079330A

    公开(公告)日:1978-03-14

    申请号:US746336

    申请日:1976-12-01

    摘要: The inventive system demodulates angle-modulated signals. A tracking band-pass filter responds to an input angle-modulated wave signal. The tracking filter has a pass band with a center frequency controlled by a control signal. A first amplitude limiter limits the amplitude of the input angle-modulated wave signal. A differentiation circuit establishes a 90.degree. phase difference between a signal passing through the tracking band-pass filter and a signal passing through the amplitude limiter. A phase comparator responds to an input with the two signals with a 90.degree. phase difference therebetween and produces an output error signal in accordance with this phase difference. This output error signal is supplied as the control signal to the tracking band-pass filter. This output error signal is also passed through a low pass filter to produce the demodulated signal.

    摘要翻译: 本发明的系统解调角度调制信号。 跟踪带通滤波器响应输入角度调制波信号。 跟踪滤波器具有通过控制信号控制的中心频率的通带。 第一幅度限制器限制输入角度调制波信号的幅度。 差分电路在通过跟踪带通滤波器的信号和通过幅度限制器的信号之间建立90°的相位差。 相位比较器响应输入,其中两个信号之间的相位差为90°,并根据该相位差产生输出误差信号。 该输出误差信号作为控制信号提供给跟踪带通滤波器。 该输出误差信号也通过低通滤波器以产生解调信号。

    Continuous casting system
    58.
    发明授权
    Continuous casting system 失效
    连铸系统

    公开(公告)号:US4030533A

    公开(公告)日:1977-06-21

    申请号:US686362

    申请日:1976-05-14

    IPC分类号: B22D11/12 B22D11/16 B22D11/10

    摘要: A continuous casting system provides with a foreign matter receiving gutter between two adjacent rolls to receive foreign matters dropping during the drawing operation of castings, and a foreign matter removing nozzle to wash away the foreign matter dropped on the gutter. An electromagnetic agitator of the continuous casting system is provided with a proximity switch at least at its inlet side to sense a magnetic substance approaching the agitator thereby to control the operation of the agitator, thus eliminating troubles caused by the vibration of the magnetic substance.

    摘要翻译: 连续铸造系统在两个相邻的辊之间提供接收沟槽的异物,以在铸件的拉制操作期间接收异物掉落,以及异物去除喷嘴,以清除掉在沟槽上的异物。 连续铸造系统的电磁搅拌器至少在其入口侧设置有接近开关,以感测接近搅拌器的磁性物质,从而控制搅拌器的操作,从而消除由磁性物质的振动引起的麻烦。

    Muting circuit
    60.
    发明授权
    Muting circuit 失效
    静音电路

    公开(公告)号:US3940698A

    公开(公告)日:1976-02-24

    申请号:US361218

    申请日:1973-05-17

    申请人: Yasuo Itoh

    发明人: Yasuo Itoh

    摘要: A muting circuit comprises, substantially, a gate circuit for passing or not passing input signals and a circuit for forming a control signal for controlling the gating operation of the gate circuit. The control signal forming circuit has a circuit for detecting the level of a carrier wave in the input signal. A first time constant circuit has a very small time constant .tau..sub.1. A second time constant circuit exhibits a delay time constant of .tau..sub.2 (where .tau..sub.2 >>.tau..sub.1) when a carrier wave component exists in the input and a delay time constant which becomes substantially zero when a carrier wave component does not exist. A third time constant circuit of a time constant .tau..sub.3 (where .tau..sub.3 >.tau..sub.2) is with a 180.degree. phase relationship relative to the second time constant circuit.

    摘要翻译: 静音电路基本上包括用于通过或不通过输入信号的门电路和用于形成用于控制门电路的选通操作的控制信号的电路。 控制信号形成电路具有用于检测输入信号中载波电平的电路。 第一时间常数电路具有非常小的时间常数τ1。当输入中存在载波分量时,第二时间常数电路表现出τ2的延迟时间常数(其中τ2 >>τ1)和延迟时间常数 当不存在载波分量时,其变为基本为零。 时间常数τ3(其中tau 3> tau 2)的第三次恒定电路相对于第二时间常数电路具有180°的相位关系。