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    Continuous casting system
    1.
    发明授权
    Continuous casting system 失效
    连铸系统

    公开(公告)号：US4030533A

    公开(公告)日：1977-06-21

    申请号：US686362

    申请日：1976-05-14

    申请人： Yasuo Itoh ,  Yoshitake Suzuki ,  Hirohiko Shibutami ,  Koichi Hirano ,  Muneo Tagami

    发明人： Yasuo Itoh ,  Yoshitake Suzuki ,  Hirohiko Shibutami ,  Koichi Hirano ,  Muneo Tagami

    IPC分类号： B22D11/12 ,  B22D11/16 ,  B22D11/10

    CPC分类号： B22D11/16 ,  B22D11/12 ,  B22D11/122

    摘要： A continuous casting system provides with a foreign matter receiving gutter between two adjacent rolls to receive foreign matters dropping during the drawing operation of castings, and a foreign matter removing nozzle to wash away the foreign matter dropped on the gutter. An electromagnetic agitator of the continuous casting system is provided with a proximity switch at least at its inlet side to sense a magnetic substance approaching the agitator thereby to control the operation of the agitator, thus eliminating troubles caused by the vibration of the magnetic substance.

    摘要翻译： 连续铸造系统在两个相邻的辊之间提供接收沟槽的异物，以在铸件的拉制操作期间接收异物掉落，以及异物去除喷嘴，以清除掉在沟槽上的异物。 连续铸造系统的电磁搅拌器至少在其入口侧设置有接近开关，以感测接近搅拌器的磁性物质，从而控制搅拌器的操作，从而消除由磁性物质的振动引起的麻烦。

    Non-volatile semiconductor memory device for storing multivalue data and readout/write-in method therefor
    6.
    发明授权
    Non-volatile semiconductor memory device for storing multivalue data and readout/write-in method therefor 失效
    用于存储多值数据和其读出/写入方法的非易失性半导体存储器件

    公开(公告)号：US5751634A

    公开(公告)日：1998-05-12

    申请号：US647629

    申请日：1996-05-15

    申请人： Yasuo Itoh

    发明人： Yasuo Itoh

    IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C7/00

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5642 ,  G11C2211/5647

    摘要： Memory cells each for storing 2-bit data are connected to a bit line. First and second flip-flop circuits are coupled to the bit line. The first flip-flop circuit holds the lower bit of 2-bit data read out from or written into the memory cell and the second flip-flop circuit holds the upper bit of 2-bit data read out from or written into the memory cell. At the data readout time, the upper bit is first read out from the memory cell and then the lower bit is read out from the memory cell. At the data writing time, the upper bit is first written into the memory cell and then the lower bit is written into the memory cell.

    摘要翻译： 每个用于存储2位数据的存储单元连接到位线。 第一和第二触发器电路耦合到位线。 第一触发器电路保持从存储单元读出或写入存储单元的2位数据的低位，并且第二触发器电路保持从存储单元读出或写入存储单元的2位数据的高位。 在数据读出时，首先从存储单元读出高位，然后从存储单元读出低位。 在数据写入时，首先将高位写入存储单元，然后将较低位写入存储单元。

    Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells
    7.
    发明授权
    Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells 失效
    具有用于验证写入存储单元的数据的验证模式的非易失性半导体存储器件

    公开(公告)号：US5557568A

    公开(公告)日：1996-09-17

    申请号：US427265

    申请日：1995-04-24

    申请人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

    发明人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

    IPC分类号： G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

    CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/3454 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1048

    摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element, and a transistor charges the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit for connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

    摘要翻译： 非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。 位线通过开关元件连接到触发器电路，晶体管对位线进行充电。 连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值 在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位， 在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。 一种数据设定电路，用于在触发电路的第一和第二信号节点之一连接到预定电位，当位线在验证模式下处于充电电位时，从而将触发器电路设置在第二状态，而与 在验证模式之前的状态。

    Semiconductor memory system with dynamic random access memory cells
    10.
    发明授权
    Semiconductor memory system with dynamic random access memory cells 失效
    具有动态随机存取存储单元的半导体存储器系统

    公开(公告)号：US4800530A

    公开(公告)日：1989-01-24

    申请号：US85086

    申请日：1987-08-13

    申请人： Yasuo Itoh ,  Fumio Horiguchi ,  Shigeyoshi Watanabe ,  Kazunori Ohuchi ,  Mitsugi Ogura

    发明人： Yasuo Itoh ,  Fumio Horiguchi ,  Shigeyoshi Watanabe ,  Kazunori Ohuchi ,  Mitsugi Ogura

    IPC分类号： G11C11/40 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22

    CPC分类号： G11C7/22 ,  G11C7/00 ,  G11C7/1033

    摘要： A dynamic random access memory system comprises first and second memory banks. A plurality of memory cells connected to a word line are grouped into first and second groups. The first group is arranged in the first memory bank and the second group is arranged in the second memory bank. Read/write means is provided in which each n bits from and to the first group and each n bits from and to the second group are read and written alternatively. Each bit is read and written in synchronism with the toggles of a column address strobe signal.

    摘要翻译： 动态随机存取存储器系统包括第一和第二存储体。 连接到字线的多个存储单元被分组为第一组和第二组。 第一组布置在第一存储体中，第二组布置在第二存储体中。 提供读/写装置，其中从第一组的每个n位和从第二组的每个n位和第二组的每个n位被交替地读取和写入。 每个位与列地址选通信号的切换同步读写。