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公开(公告)号：US20090134388A1
公开(公告)日：2009-05-28
申请号：US12203409
申请日：2008-09-03
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/823814 , H01L29/665 , H01L29/7833
摘要： A semiconductor device having a metal insulator semiconductor field effect transistor (MISFET) with interface resistance-reduced source/drain electrodes is disclosed. This device includes a p-type MISFET formed on a semiconductor substrate. The p-MISFET has a channel region in the substrate, a gate insulating film on the channel region, a gate electrode on the gate insulating film, and a pair of laterally spaced-apart source and drain electrodes on both sides of the channel region. These source/drain electrodes are each formed of a nickel (Ni)-containing silicide layer. The p-MISFET further includes an interface layer which is formed on the substrate side of an interface between the substrate and each source/drain electrode. This interface layer contains magnesium (Mg), calcium (Ca) or barium (Ba) therein. A fabrication method of the semiconductor device is also disclosed.
摘要翻译： 公开了一种具有金属绝缘体半导体场效应晶体管（MISFET）的半导体器件，具有接口电阻降低的源/漏电极。 该器件包括形成在半导体衬底上的p型MISFET。 p-MISFET在衬底中具有沟道区，沟道区上的栅极绝缘膜，栅极绝缘膜上的栅电极，以及沟道区两侧的一对侧向间隔开的源极和漏极。 这些源极/漏极各自由含镍（Ni）的硅化物层形成。 p-MISFET还包括界面层，该界面层形成在基板和每个源极/漏极之间的界面的基板侧上。 该界面层中含有镁（Mg），钙（Ca）或钡（Ba）。 还公开了半导体器件的制造方法。
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公开(公告)号：US20070249106A1
公开(公告)日：2007-10-25
申请号：US11812839
申请日：2007-06-22
IPC分类号： H01L21/8238 , H01L21/84
CPC分类号： H01L21/823835 , H01L21/823842
摘要： It is possible to provide a semiconductor device including a CMOS device having a gate electrode, in which the variation in threshold voltage is little. There are a p-channel MIS transistor and a n-channel MIS transistor which are provided in a semiconductor substrate, and in a region of a gate electrode of the p-channel MIS transistor at least 1 nm or less apart from the interface with a gate insulating film, the oxygen concentration is 1020 cm−3 or more and 1022 cm−3 or less.
摘要翻译： 可以提供一种包括具有门电极的CMOS器件的半导体器件，其中阈值电压的变化很小。 存在设置在半导体衬底中的p沟道MIS晶体管和n沟道MIS晶体管，并且在p沟道MIS晶体管的栅电极的区域中，除了与 栅极绝缘膜，氧浓度为10〜30厘米-3以上且10〜22厘米-3以上或 减。
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公开(公告)号：US20070210351A1
公开(公告)日：2007-09-13
申请号：US11526637
申请日：2006-09-26
IPC分类号： H01L29/76
CPC分类号： H01L21/823835 , H01L27/1203 , H01L29/785
摘要： According to an aspect of the invention, a semiconductor device comprises: a N-channel MIS transistor comprising; a p-type semiconductor layer; a first gate insulation layer formed on the p-type semiconductor layer; a first gate electrode formed on the first gate insulation layer; and a first source-drain region formed in the p-type semiconductor layer where the first gate electrode is sandwiched along a direction of gate length. The first gate electrode comprises a crystal phase including a cubic crystal of NiSi2 which has a lattice constant of 5.39 angstroms to 5.40 angstroms.
摘要翻译： 根据本发明的一个方面，半导体器件包括：N沟道MIS晶体管，包括： p型半导体层; 形成在p型半导体层上的第一栅绝缘层; 形成在所述第一栅极绝缘层上的第一栅电极; 以及形成在p型半导体层中的第一源极 - 漏极区，其中第一栅极沿着栅极长度的方向被夹持。 第一栅电极包括晶体相，其包括具有5.39埃至5.40埃的晶格常数的NiSi 2 N 3的立方晶体。
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公开(公告)号：US20070057335A1
公开(公告)日：2007-03-15
申请号：US11377438
申请日：2006-03-17
IPC分类号： H01L29/94
CPC分类号： H01L21/823857 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L29/49 , H01L29/4975 , H01L29/665 , H01L29/785
摘要： It is made possible to control the effective work function of the gate electrode so that the transistor can have an optimum operating threshold voltage. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided on the semiconductor substrate; a gate electrode provided on the gate insulating film; source/drain regions provided in the semiconductor substrate on both sides of the gate electrode; and a layer which is provided at an interface between the gate electrode and the gate insulating film, and contains an element having an electronegativity different from those of elements constituting the gate electrode and the gate insulating film.
摘要翻译： 可以控制栅电极的有效功函数，使得晶体管能够具有最佳的工作阈值电压。 半导体器件包括：半导体衬底; 设置在所述半导体基板上的栅极绝缘膜; 设置在所述栅极绝缘膜上的栅电极; 源极/漏极区域设置在栅电极两侧的半导体衬底中; 以及设置在栅极电极和栅极绝缘膜之间的界面处的层，并且包含与构成栅极电极和栅极绝缘膜的元件的电负性不同的元件。
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公开(公告)号：US20060180870A1
公开(公告)日：2006-08-17
申请号：US11299773
申请日：2005-12-13
IPC分类号： H01L29/76
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
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公开(公告)号：US20060038229A1
公开(公告)日：2006-02-23
申请号：US11116327
申请日：2005-04-28
申请人： Yoshinori Tsuchiya , Junji Koga
发明人： Yoshinori Tsuchiya , Junji Koga
IPC分类号： H01L21/00 , H01L27/01 , H01L21/84 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/823814 , H01L21/26513 , H01L21/28061 , H01L21/823835 , H01L21/84 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66643 , H01L29/7839
摘要： Disclosed is a semiconductor device comprising a semiconductor substrate having isolation regions, and a MIS transistor comprising a gate electrode formed above the semiconductor substrate with a gate insulating film interposed therebetween, and a pair of contact layers formed on the semiconductor substrate sandwiching the gate electrode, the contact layers having an interfacial layer at an interface between the semiconductor substrate and the contact layers, the interfacial layer comprising a metal silicide containing at least one selected from a group consisting of Er, Gd, Tb, Dy, Ho, Tm, Yb, Lu, and Pt.
摘要翻译： 公开了一种半导体器件，其包括具有隔离区域的半导体衬底，以及MIS晶体管，其包括形成在半导体衬底上方的栅电极，栅极绝缘膜插入其间的栅极电极和形成在夹持栅电极的半导体衬底上的一对接触层， 所述接触层在所述半导体衬底和所述接触层之间的界面处具有界面层，所述界面层包含含有选自Er，Gd，Tb，Dy，Ho，Tm，Yb中的至少一种的金属硅化物， 卢和铂。
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公开(公告)号：US08587060B2
公开(公告)日：2013-11-19
申请号：US13404349
申请日：2012-02-24
申请人： Yoshinori Tsuchiya
发明人： Yoshinori Tsuchiya
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/78 , H01L21/046 , H01L21/0485 , H01L29/045 , H01L29/1608 , H01L29/51 , H01L29/66068 , H01L29/7394 , H01L29/7827
摘要： A semiconductor device according to the present embodiment includes a semiconductor substrate having a first n-type silicon carbide layer and a second n-type silicon carbide layer, a first p-type impurity region formed in the n-type silicon carbide layer, a first n-type impurity region of 4H—SiC structure formed in the n-type silicon carbide layer, a second n-type impurity region of 3C—SiC structure formed in the n-type silicon carbide layer having a depth shallower than the first n-type impurity region, a gate insulating film, a gate electrode formed on the gate insulating film, and a metallic silicide layer formed above the first n-type impurity region and having a bottom portion and a side surface portion such that the second n-type impurity region is sandwiched between the first n-type impurity region and at least the side surface portion.
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公开(公告)号：US07986014B2
公开(公告)日：2011-07-26
申请号：US12654490
申请日：2009-12-22
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
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公开(公告)号：US07977182B2
公开(公告)日：2011-07-12
申请号：US12323770
申请日：2008-11-26
IPC分类号： H01L21/8238 , H01L29/04 , H01L29/10 , H01L31/036 , H01L21/285
CPC分类号： H01L29/4975 , H01L21/26506 , H01L21/28097 , H01L21/28518 , H01L21/28537 , H01L21/324 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L23/485 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.
摘要翻译： 这里描述的是通过降低电极的接触电阻来制造实现更高性能的半导体器件的方法。 在该方法中，在半导体衬底上形成栅极绝缘膜，栅电极。 第一金属是沉积衬底，并且通过使第一金属和半导体衬底通过第一热处理而彼此反应，在半导体衬底的表面上形成金属半导体化合物层。 将具有等于或大于Si原子量的质量的离子注入到金属半导体化合物层中。 第二金属沉积在金属半导体化合物层上。 通过使第二金属通过第二热处理使金属半导体化合物层扩散而使第二金属在金属半导体化合物层和半导体基板之间的界面分离而形成界面层。
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公开(公告)号：US07768077B2
公开(公告)日：2010-08-03
申请号：US12631891
申请日：2009-12-07
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28097 , H01L21/823835 , H01L21/823857 , H01L27/092 , H01L29/495 , H01L29/4975 , H01L29/517 , H01L29/665
摘要： A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.
摘要翻译： 半导体器件包括：n沟道MIS晶体管和p沟道MIS晶体管。 n沟道MIS晶体管包括：具有在第一源极/漏极区之间的p型半导体区域上形成的非晶层或外延层的第一栅极绝缘膜; 以及具有形成有第一金属层和第一化合物层的堆叠结构的第一栅电极。 第一金属层形成在第一栅极绝缘膜上，由功函数为4.3eV以下的第一金属构成，第一金属层形成在第一金属层上，并且含有第二金属和 IV族半导体。 第二种金属与第一种金属不同。 P沟道MIS晶体管包括具有第二化合物层的第二栅电极，第二化合物层含有与第一化合物层相同组成的化合物。
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