公开(公告)号：US08217446B2

公开(公告)日：2012-07-10

申请号：US12559865

申请日：2009-09-15

申请人： Yoshiaki Fukuzumi ,  Masaru Kito ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Masaru Kito ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： Each of memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate; a charge storage layer formed to surround a side surface of the columnar portions; and a first conductive layer formed to surround the charge storage layer. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; a gate insulating layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the gate insulating layer. An effective impurity concentration of the second semiconductor layer is less than or equal to an effective impurity concentration of the first semiconductor layer.

摘要翻译： 每个存储器串都具有第一半导体层，该第一半导体层具有相对于衬底在垂直方向上延伸的一对柱状部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕电荷存储层的第一导电层。 每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 形成为围绕所述第二半导体层的侧表面的栅极绝缘层; 以及形成为围绕所述栅极绝缘层的第二导电层。 第二半导体层的有效杂质浓度小于或等于第一半导体层的有效杂质浓度。

公开(公告)号：US08199573B2

公开(公告)日：2012-06-12

申请号：US12694677

申请日：2010-01-27

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Tomoko Fujiwara ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshimasa Mikajiri ,  Shigeto Oota ,  Ryouhei Kirisawa ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Tomoko Fujiwara ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshimasa Mikajiri ,  Shigeto Oota ,  Ryouhei Kirisawa ,  Hideaki Aochi

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/34 ,  G11C5/02 ,  G11C16/26

摘要： A nonvolatile semiconductor memory device comprises: a bit line; a source line; a memory string having a plurality of electrically data-rewritable memory transistors connected in series; a first select transistor provided between one end of the memory string and the bit line; a second select transistor provided between the other end of the memory string and the source line; and a control circuit configured to control a read operation. A plurality of the memory strings connected to one bit line via a plurality of the first select transistors. During reading of data from a selected one of the memory strings, the control circuit renders conductive the first select transistor connected to an unselected one of the memory strings and renders non-conductive the second select transistor connected to unselected one of the memory strings.

摘要翻译： 非易失性半导体存储器件包括：位线; 源线; 具有串联连接的多个电数据可重写存储晶体管的存储器串; 设置在存储器串的一端和位线之间的第一选择晶体管; 设置在存储器串的另一端与源极线之间的第二选择晶体管; 以及控制电路，被配置为控制读取操作。 经由多个第一选择晶体管连接到一个位线的多个存储器串。 在从选择的一个存储器串读取数据期间，控制电路使连接到未选择的一个存储器串的第一选择晶体管导通，并且使第二选择晶体管连接到未选择的一个存储器串。

公开(公告)号：US08198667B2

公开(公告)日：2012-06-12

申请号：US12808321

申请日：2008-12-25

申请人： Takuji Kuniya ,  Yosuke Komori ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Hideaki Aochi

发明人： Takuji Kuniya ,  Yosuke Komori ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Hideaki Aochi

IPC分类号： H01L27/115 ,  H01L21/8247 ,  H01L29/792 ,  H01L29/788

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7926

摘要： A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film.

摘要翻译： 通过在硅衬底上交替层叠多个电介质膜和电极膜来形成层叠体。 接下来，在层叠体中形成在层叠方向上延伸的贯通孔。 接下来，进行选择性氮化处理，以在对应于电极膜的通孔的内表面的区域中选择性地形成由氮化硅制成的电荷层。 接下来，进行高压氧化处理以在电荷层和电极膜之间形成由氧化硅制成的阻挡层。 接下来，在通孔的内侧表面上形成由氧化硅制成的隧道层。 因此，可以制造其中为每个电极膜分裂电荷层的快闪存储器。

公开(公告)号：US08169826B2

公开(公告)日：2012-05-01

申请号：US12726858

申请日：2010-03-18

申请人： Tomoo Hishida ,  Yoshihisa Iwata ,  Megumi Ishiduki ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Tomoo Hishida ,  Yoshihisa Iwata ,  Megumi Ishiduki ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： G11C16/04 ,  H01L29/792 ,  H01L29/66

CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C5/04 ,  G11C16/0483 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device comprises: a plurality of first memory strings; a first select transistor having one end thereof connected to one end of the first memory strings; a first line commonly connected to the other end of a plurality of the first select transistors; a switch circuit having one end thereof connected to the first line; and a second line commonly connected to the other end of a plurality of the switch circuits. The switch circuit controls electrical connection between the second line and the first line.

摘要翻译： 非易失性半导体存储器件包括：多个第一存储器串; 第一选择晶体管，其一端连接到第一存储器串的一端; 通常连接到多个第一选择晶体管的另一端的第一线; 开关电路，其一端连接到第一线; 以及通常连接到多个开关电路的另一端的第二线。 开关电路控制第二线和第一线之间的电连接。

公开(公告)号：US08154068B2

公开(公告)日：2012-04-10

申请号：US12647836

申请日：2009-12-28

申请人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Masaru Kidoh ,  Yoshiaki Fukuzumi

发明人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Masaru Kidoh ,  Yoshiaki Fukuzumi

IPC分类号： H01L29/76

CPC分类号： H01L27/11578 ,  H01L27/0688 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： Each of memory strings comprising: a first semiconductor layer having a pair of columnar portions extending in a vertical direction to a substrate and a joining portion formed to join lower ends of the pair of columnar portions; an electric charge accumulation layer formed to surround a side surface of the first semiconductor layer; and a first conductive layer formed to surround a side surface of the electric charge accumulation layer. The columnar portions are aligned at a first pitch in a first direction orthogonal to the vertical direction, and arranged in a staggered pattern at a second pitch in a second direction orthogonal to the vertical and first directions. The first conductive layers are configured to be arranged at the first pitch in the first direction, and extend to curve in a wave-like fashion in the second direction along the staggered-pattern arrangement.

摘要翻译： 每个存储串包括：第一半导体层，具有在垂直方向上延伸到基板的一对柱状部分和形成为连接该一对柱状部分的下端的接合部分; 形成为包围第一半导体层的侧面的电荷蓄积层; 以及形成为围绕电荷蓄积层的侧表面的第一导电层。 柱状部分在垂直于垂直方向的第一方向上以第一间距排列，并且在垂直于垂直方向和第一方向的第二方向上以第二间距布置成交错图案。 第一导电层被配置为沿着第一方向以第一间距布置，并且沿着交错图案布置在第二方向上以波浪形的方式延伸。

公开(公告)号：US08048798B2

公开(公告)日：2011-11-01

申请号：US12389977

申请日：2009-02-20

申请人： Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L21/4763

CPC分类号： H01L27/11578 ,  H01L21/8221 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A method for manufacturing a nonvolatile semiconductor storage device, including: forming a first conductive layer so that it is sandwiched in an up-down direction by first insulating layers; forming a first hole so that it penetrates the first insulating layers and the first conductive layer; forming a first side wall insulating layer on a side wall facing the first hole; forming a sacrificing layer so that the sacrificing layer infills the first hole; forming a second conductive layer on an upper layer of the sacrificing layer so that the second conductive layer is sandwiched by the second insulating layer in an up-down direction; forming a second hole on a position which matches with the first hole so that the second hole penetrates the second insulating layer and the second conductive layer; forming a second side wall insulating layer on a side wall facing the second hole; removing the sacrificing layer after the formation of the second side wall insulating layer; and forming a semiconductor layer so that the semiconductor layer infills the first hole and the second hole after the removal of the sacrificing layer.

摘要翻译： 一种制造非易失性半导体存储装置的方法，包括：形成第一导电层，使其通过第一绝缘层沿上下方向夹持; 形成第一孔，使其穿透第一绝缘层和第一导电层; 在面向所述第一孔的侧壁上形成第一侧壁绝缘层; 形成牺牲层，使牺牲层填充第一孔; 在牺牲层的上层上形成第二导电层，使得第二导电层在上下方向上被第二绝缘层夹持; 在与所述第一孔匹配的位置上形成第二孔，使得所述第二孔穿过所述第二绝缘层和所述第二导电层; 在面向所述第二孔的侧壁上形成第二侧壁绝缘层; 在形成第二侧壁绝缘层之后去除牺牲层; 以及形成半导体层，使得半导体层在去除牺牲层之后填充第一孔和第二孔。

公开(公告)号：US08013383B2

公开(公告)日：2011-09-06

申请号：US12389856

申请日：2009-02-20

申请人： Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Akihiro Nitayama ,  Hitoshi Ito ,  Yasuyuki Matsuoka

发明人： Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Akihiro Nitayama ,  Hitoshi Ito ,  Yasuyuki Matsuoka

IPC分类号： H01L29/792

CPC分类号： H01L27/105 ,  H01L27/0688 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

摘要： A nonvolatile semiconductor storage device has a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series. The memory string has a columnar semiconductor layer extending in a direction perpendicular to a substrate; a conductive layer formed so as to sandwich a charge storing layer in cooperation with the columnar semiconductor layer; and a metal layer formed so as to be in contact with the top face of the conductive layer.

摘要翻译： 非易失性半导体存储装置具有串联连接多个电可重写存储单元的多个存储串。 存储器串具有在垂直于衬底的方向上延伸的柱状半导体层; 形成为与柱状半导体层配合地夹着电荷存储层的导电层; 以及形成为与导电层的顶面接触的金属层。

公开(公告)号：US20110103149A1

公开(公告)日：2011-05-05

申请号：US12851002

申请日：2010-08-05

申请人： Ryota KATSUMATA ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Ryota KATSUMATA ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/06 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a stacked body, a through-hole, a semiconductor pillar, and a charge storage film. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in the through-hole. The charge storage film is provided between the electrode films and the semiconductor pillar. Memory cells are formed at each intersection between the electrode films and the semiconductor pillar. The control circuit writs a first value to at least some of the memory cells, performs an erasing operation of the first value from the memory cell written with the first value, reads data stored in the memory cell having undergone the erasing operation, and sets the memory cell to be unusable in a case that the first value is read from the memory cell.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储单元阵列和控制电路。 存储单元阵列包括层叠体，通孔，半导体柱和电荷存储膜。 层叠体包括交替层叠有多个电极膜的多个绝缘膜。 通孔形成在堆叠体中以沿堆叠方向对齐。 半导体柱埋在通孔中。 电荷存储膜设置在电极膜和半导体柱之间。 在电极膜和半导体柱之间的每个交叉处形成存储单元。 控制电路将第一值写入至少部分存储单元，从写入第一值的存储单元执行第一值的擦除操作，读取存储在经过擦除操作的存储单元中的数据，并将 在从存储器单元读取第一值的情况下，存储器单元不可用。

公开(公告)号：US20110019480A1

公开(公告)日：2011-01-27

申请号：US12727854

申请日：2010-03-19

申请人： Masaru KITO ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Hideaki Aochi

发明人： Masaru KITO ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Hideaki Aochi

IPC分类号： G11C16/02 ,  H01L29/51

CPC分类号： H01L29/792 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; a first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer to electrically connect the first and second semiconductor pillars; a connection portion conductive layer opposing the connection portion semiconductor layer; a memory layer, an inner insulating film, and an outer insulating film provided between the first and second semiconductor layers and the electrode films and between the connection portion semiconductor layer and the connection portion conductive layer. At least a portion of a face of the connection portion conductive layer opposing the outer insulating film is a curved surface having a recessed configuration on a side of the outer insulating film.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠结构单元，其包括交替层叠有电极间绝缘膜的电极膜; 第一和第二半导体柱刺穿堆叠的结构单元; 电连接第一和第二半导体柱的连接部分半导体层; 与连接部分半导体层相对的连接部分导电层; 设置在第一和第二半导体层与电极膜之间以及连接部分半导体层和连接部分导电层之间的记忆层，内部绝缘膜和外部绝缘膜。 连接部导电层的与外绝缘膜相对的面的至少一部分是在外绝缘膜一侧具有凹陷构造的曲面。

公开(公告)号：US20110018052A1

公开(公告)日：2011-01-27

申请号：US12820371

申请日：2010-06-22

申请人： Tomoko Fujiwara ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Tomoko Fujiwara ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/792 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structure, a semiconductor pillar, a memory layer and an outer insulating film. The stacked structure includes a plurality of electrode films and a plurality of interelectrode insulating films alternately stacked in a first direction. The semiconductor pillar pierces the stacked structure in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The outer insulating film is provided between the electrode films and the memory layer. The device includes a first region and a second region. An outer diameter of the outer insulating film along a second direction perpendicular to the first direction in the first region is larger than that in the second region. A thickness of the outer insulating film along the second direction in the first region is thicker than that in the second region.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括堆叠结构，半导体柱，存储层和外部绝缘膜。 堆叠结构包括沿第一方向交替堆叠的多个电极膜和多个电极间绝缘膜。 半导体柱沿第一方向刺穿层叠结构。 存储层设置在电极膜和半导体柱之间。 外绝缘膜设置在电极膜和存储层之间。 该装置包括第一区域和第二区域。 沿着与第一区域的第一方向垂直的第二方向的外绝缘膜的外径大于第二区域的外径。 第一区域中沿着第二方向的外绝缘膜的厚度比第二区域厚。