公开(公告)号：US20220037466A1

公开(公告)日：2022-02-03

申请号：US16943569

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Haitao Liu

IPC: H01L29/10 ,  H01L27/108

Abstract: Systems, methods and apparatus are provided for forming layers of a first dielectric material, a semiconductor material, and a second dielectric material in repeating iterations vertically to form a vertical stack and forming a vertical opening using an etchant process to expose vertical sidewalls in the vertical stack. A seed material that is selective to the semiconductor material is deposited over the vertical stack and the vertical sidewalls in the vertical stack and the seed material is processed such that the seed material advances within the semiconductor material such that it transforms a crystalline structure of a portion of the semiconductor material.

公开(公告)号：US20220037324A1

公开(公告)日：2022-02-03

申请号：US16943494

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3205 ,  H01L29/66

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the horizontally oriented digit lines by a dielectric.

公开(公告)号：US20220028903A1

公开(公告)日：2022-01-27

申请号：US16934607

申请日：2020-07-21

Applicant: Micron Technology, Inc.

Inventor： Yi Fang Lee ,  Jaydip Guha ,  Lars P. Heineck ,  Kamal M. Karda ,  Si-Woo Lee ,  Terrence B. McDaniel ,  Scott E. Sills ,  Kevin J. Torek ,  Sheng-Wei Yang

IPC: H01L27/12 ,  H01L21/84

Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

公开(公告)号：US20200294852A1

公开(公告)日：2020-09-17

申请号：US16299469

申请日：2019-03-12

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee

IPC: H01L21/768 ,  H01L21/308 ,  H01L27/108

Abstract: A method of forming conductive vias of integrated circuitry comprises forming first openings in a first masking material, with the first openings being spaced along a line passing across the first openings. Sidewalls of the first openings are lined with a second masking material to form a ring within individual of the first openings and a second opening within the individual first openings radially inside of the ring. The first masking material is removed along the line to form a void space between immediately-adjacent of the rings. A mask is formed that comprises the rings and a third opening in third masking material, with the third opening extending along the line above and across multiple of the rings and multiple of the second openings. The mask is used as an etch mask while etching into substrate material that is exposed through the third opening to form contact openings in the substrate material that are spaced along the line. Conductive material is formed in the contact openings to form conductive vias.

公开(公告)号：US20200027486A1

公开(公告)日：2020-01-23

申请号：US16040337

申请日：2018-07-19

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Si-Woo Lee

IPC: G11C5/10 ,  G11C11/401 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly which has digit-line-contact-regions laterally spaced from one another by intervening regions. Non-conductive-semiconductor-material is over the intervening regions. Openings extend through the non-conductive-semiconductor-material to the digit-line-contact-regions. Conductive-semiconductor-material-interconnects are within the openings and are coupled with the digit-line-contact-regions. Upper surfaces of the conductive-semiconductor-material-interconnects are beneath a lower surface of the non-conductive-semiconductor-material. Metal-containing-digit-lines are over the non-conductive-semiconductor-material. Conductive regions extend downwardly from the metal-containing-digit-lines to couple with the conductive-semiconductor-material-interconnects. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US09761590B1

公开(公告)日：2017-09-12

申请号：US15162028

申请日：2016-05-23

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Sourabh Dhir ,  Rajesh N. Gupta ,  Sanh D. Tang ,  Si-Woo Lee ,  Haitao Liu

IPC: H01L23/52 ,  H01L27/108 ,  H01L29/06 ,  H01L27/088 ,  H01L23/528 ,  G11C11/4078

CPC classification number: H01L27/10826 ,  G11C7/02 ,  G11C11/404 ,  G11C11/4078 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.

公开(公告)号：US20250159865A1

公开(公告)日：2025-05-15

申请号：US18933964

申请日：2024-10-31

Applicant: Micron Technology, Inc.

Inventor： Yuanzhi Ma ,  Scott E. Sills ,  Si-Woo Lee

IPC: H10B12/00 ,  H10B53/20 ,  H10B53/30

Abstract: Methods, systems, and devices for self-aligned capacitors for three-dimensional memory systems are described. For example, a capacitor of a memory cell may include multiple interfaces (e.g., concentric interfaces, dielectric interfaces, interfaces at different relative radial positions from an axis of the capacitor) between material portions of a first electrode and a second electrode, each across a respective portion of a dielectric material. A separating dielectric feature may be included between the capacitor and a cell selection transistor of the memory cell, which may support self-alignment of features of the capacitor with features of the cell selection transistor (e.g., self-alignment for fabrication operations associated with forming the capacitor).

公开(公告)号：US20240260254A1

公开(公告)日：2024-08-01

申请号：US18403103

申请日：2024-01-03

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Si-Woo Lee ,  Chandra Mouli

IPC: H10B12/00 ,  H01L23/528 ,  H01L29/423

CPC classification number: H10B12/33 ,  H01L23/5283 ,  H01L29/42392 ,  H10B12/03 ,  H10B12/482 ,  H10B12/488

Abstract: Methods, apparatuses, and systems related to a memory device having transistor body contacts that extend vertically across stacked circuit layers and connect to body portions of data access transistors are described. A memory device may include storage cells and corresponding access circuits on each of the stacked layers. The vertically extending transistor body contacts may provide a route for leakage away from data storage circuits when the data access transistors are off.

公开(公告)号：US12004341B2

公开(公告)日：2024-06-04

申请号：US17886917

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Sangmin Hwang ,  Si-Woo Lee

IPC: H10B12/00

CPC classification number: H10B12/36 ,  H10B12/056 ,  H10B12/50

Abstract: A variety of applications can include apparatus having a recessed channel FinFET. The recessed channel FinFET can include one or more fin structures between the source region and the drain region, where the one or more fin structures are recessed from a top level of the source region and from a top level of the drain region. The recessed channel FinFET can include a gate recessed from the top level of a source region and a drain region, where the gate can be separated from tip regions of the fin structures by a gate dielectric defining a channel between the source region and the drain region. Recessed channel FinFETs can be structured in a periphery to an array of a memory device and can be fabricated in a process merged with forming access lines to the array.

公开(公告)号：US20240172420A1

公开(公告)日：2024-05-23

申请号：US18428581

申请日：2024-01-31

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Sangmin Hwang

IPC: H10B12/00 ,  G11C11/402 ,  H01L25/065 ,  H01L27/06

CPC classification number: H10B12/36 ,  G11C11/4023 ,  H01L25/0657 ,  H01L27/0688 ,  H10B12/056

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and vertically oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.