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    SELECTIVE PARTITIONING OF SETS OF PAGES PROGRAMMED TO MEMORY DEVICE
    51.
    发明申请
    SELECTIVE PARTITIONING OF SETS OF PAGES PROGRAMMED TO MEMORY DEVICE 有权

    公开(公告)号：US20220083243A1

    公开(公告)日：2022-03-17

    申请号：US16948305

    申请日：2020-09-11

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Karl D. Schuh ,  Jiangang Wu ,  Mustafa N. Kaynak ,  Devin M. Batutis ,  Xiangang Luo

    IPC: G06F3/06

    Abstract: A system includes a memory device having multiple of dice and a processing device operatively coupled to the memory device. The processing device performs operations including receiving memory operations to program sets of pages of data across at least a subset of the plurality of dice and identifying a plurality of the sets of pages experiencing a variation in a data state metric satisfying a threshold criterion. The operations further include partitioning, into a set of partitions, a set of pages of the plurality of the sets of pages, programming the set of partitions to the plurality of dice, and storing, in a metadata table, at least one bit to indicate that the first set of pages is partitioned.

    MANAGING STORAGE OF MULTIPLE PLANE PARITY DATA IN A MEMORY SUB-SYSTEM
    52.
    发明申请
    MANAGING STORAGE OF MULTIPLE PLANE PARITY DATA IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20210200637A1

    公开(公告)日：2021-07-01

    申请号：US16854429

    申请日：2020-04-21

    Applicant: Micron Technology, Inc.

    Inventor： Xiangang Luo ,  Jianmin Huang ,  Lakshmi Kalpana K. Vakati ,  Harish R. Singidi

    IPC: G06F11/10 ,  G06F3/06

    Abstract: Host data to be written to a storage area including a set of multiple planes of a memory device is received. A first parity generation operation based on a portion of the set of multiple planes of the host data to generate a set of multi-plane parity data is executed. The set of multi-plane parity data is stored in in a cache memory of a controller of a memory sub-system. A second parity generation operation based on the set of the multiple planes of the host data to generate a set of multi-page parity data is executed. The set of multi-page parity data in the cache memory of the controller of the memory sub-system is stored. A data recovery operation is performed based on the set of multi-plane parity data and the set of multi-page parity data.

    PARITY PROTECTION
    53.
    发明申请
    PARITY PROTECTION 有权

    公开(公告)号：US20210191807A1

    公开(公告)日：2021-06-24

    申请号：US16723836

    申请日：2019-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Chun Sum Yeung ,  Falgun G. Trivedi ,  Harish Reddy Singidi ,  Xiangang Luo ,  Preston Allen Thomson ,  Ting Luo ,  Jianmin Huang

    IPC: G06F11/10 ,  G06F11/07 ,  G06F12/02 ,  G06F12/0882

    Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.

    READ ERROR RECOVERY
    54.
    发明申请
    READ ERROR RECOVERY 有权

    公开(公告)号：US20210132823A1

    公开(公告)日：2021-05-06

    申请号：US17051961

    申请日：2019-05-07

    Applicant: Micron Technology, Inc.

    Inventor： Xiangang Luo ,  Harish Reddy Singidi ,  Ting Luo ,  Kishore Kumar Miuchherla

    IPC: G06F3/06

    Abstract: Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system and performing error recovery for the set of CWs using a set of error handing (EH) steps until each CW of the set of CWs are indicated as correctable in the error recovery data structure. The error recovery can include determining if each CW of the set of CWs is correctable by an EH step, storing indications of CWs determined correctable by the EH step in the error recovery data structure, determining if one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.

    Multiple memory devices having parity protection
    55.
    发明授权
    Multiple memory devices having parity protection 有权

    公开(公告)号：US10789126B2

    公开(公告)日：2020-09-29

    申请号：US16155573

    申请日：2018-10-09

    Applicant: Micron Technology, Inc.

    Inventor： Harish Reddy Singidi ,  Xiangang Luo ,  Preston Thomson ,  Michael G. McNeeley

    IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06

    Abstract: A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.

    READ DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING
    58.
    发明公开
    READ DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING 审中-公开

    公开(公告)号：US20240168879A1

    公开(公告)日：2024-05-23

    申请号：US18386760

    申请日：2023-11-03

    Applicant: Micron Technology, Inc.

    Inventor： Akira Goda ,  Kishore K. Muchherla ,  Shyam Sunder Raghunathan ,  Leo Raimondo ,  Jung Sheng Hoei ,  Xiangang Luo ,  Ashutosh Malshe ,  Jianmin Huang

    IPC: G06F12/02

    CPC classification number: G06F12/0246

    Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells each comprising: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is configured to determine a cumulative amount of read disturb stress experienced by the first erase block by monitoring read disturb stress experienced by the first erase block due to: read operations performed on the first erase block; read operations performed on the second erase block; and program verify operations performed on the second erase block. The controller can perform an action on the first erase block responsive to the cumulative amount of read disturb stress experienced by the first erase block meeting a criteria.

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