公开(公告)号：US20200264950A1

公开(公告)日：2020-08-20

申请号：US16792820

申请日：2020-02-17

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F11/10 ,  G06F11/07 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.

公开(公告)号：US20250077345A1

公开(公告)日：2025-03-06

申请号：US18775974

申请日：2024-07-17

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Joseph G. Garofalo

IPC: G06F11/10

Abstract: Methods, systems, and devices for host error control matrix are described. A host device may implement a parity check matrix for generating error control information with a relatively low likelihood that a multi-bit error in a codeword associated with the error control information is mistaken for a single-bit error. The host device may implement a parity check matrix patterned such that when the error control information is generated, there is a relatively low likelihood that an error code resulting from a comparison of the error control information will yield an indication of a single-bit error when a multi-bit error occurs. For example, the host device may compare first error control information generated for a codeword and transmitted to a memory device with second error control information generated after receiving the codeword from the memory device, and generate an error code using the results of the comparison.

公开(公告)号：US12198776B2

公开(公告)日：2025-01-14

申请号：US17648393

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/44 ,  H03K19/173

Abstract: Methods, systems, and devices for metadata storage at a memory device are described to support storage of metadata information and error control information at a memory device. The metadata information and error control information may be received at the memory device via a sideband channel and corresponding pin. For example, a set of bits received via the pin may include a subset of error control bits and a subset of metadata bits. Circuitry at the memory device may receive the set of bits via the pin and may identify metadata information and error control information within the set of bits. The circuitry may route the metadata information to a corresponding subset of memory cells and the error control information to an error control circuit, where the error control circuit may route the error control information to a corresponding subset of memory cells.

公开(公告)号：US20240345932A1

公开(公告)日：2024-10-17

申请号：US18630614

申请日：2024-04-09

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm ,  Todd Jackson Plum ,  Mark D. Ingram ,  Scott D. Van De Graaff

IPC: G06F11/30

CPC classification number: G06F11/3034 ,  G06F11/3062 ,  G06F11/3075

Abstract: Methods, systems, and devices for memory device health monitoring logic are described. In accordance with examples as disclosed herein, a memory device may include health monitoring logic configured to monitor a degradation level of the memory device. Further, the health monitoring logic may include a self-check logic to monitor the degradation level of the health monitoring logic. Using the health monitoring logic, the memory device may evaluate and store a health state of the memory device, which may be used to flag a fault in the memory device, among other responsive operations. Additionally, using the self-check logic, the memory device may evaluate and store a health state of the health monitoring logic, which may be used to flag a fault of the previously evaluated health state of the memory device. Based on the self-check flag, a host device may halt or adjust the response operations associated with the memory device.

公开(公告)号：US20240320093A1

公开(公告)日：2024-09-26

申请号：US18680470

申请日：2024-05-31

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm ,  Scott D. Van De Graaff ,  Mark D. Ingram ,  Todd Jackson Plum

IPC: G06F11/10 ,  G06F9/30 ,  G06F11/07 ,  G06F11/30

CPC classification number: G06F11/1068 ,  G06F9/30189 ,  G06F11/0772 ,  G06F11/3051

Abstract: Methods, systems, and devices for evaluation of memory device health monitoring logic are described. For example, a memory device may include health monitoring logic operable to activate certain internal health monitors of a set of multiple monitors and to communicate an output associated with the activated monitors. In a first mode of operation, the health monitoring logic may provide a single output that is generated from multiple outputs of the set of monitors. In a second mode of operation, the health monitoring logic may cycle through certain monitors (e.g., in a test mode), and may generate an output corresponding to respective active monitors as it cycles through the set of monitors. The health monitoring logic may communicate an output specific to each monitor to a host device such that the host device may evaluate an output from each monitor of the set of monitors.

公开(公告)号：US20240303158A1

公开(公告)日：2024-09-12

申请号：US18604227

申请日：2024-03-13

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/20 ,  G06F13/00 ,  G11C7/10 ,  G11C11/22 ,  G11C11/4093 ,  G11C29/52 ,  H03M13/00 ,  H03M13/19 ,  H03M13/45

CPC classification number: G06F11/1068 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  H03M13/458 ,  G06F3/0659 ,  G06F11/1052 ,  G06F11/201 ,  G06F13/00 ,  G11C7/1006 ,  G11C11/4093 ,  G11C29/52 ,  H03M13/19 ,  H03M13/6561

Abstract: Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.

公开(公告)号：US20240264767A1

公开(公告)日：2024-08-08

申请号：US18640619

申请日：2024-04-19

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0679

Abstract: Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may receive an access command transmitted to the memory device via a bus. The memory device may transmit data requested by the access command over data lines and a control signal that indicates the bus is in an active state over a control line. The control signal may be transmitted during a first unit interval of a read operation. The control signal may be configured to have a first voltage when the bus is in an idle state and a second voltage when the bus is in the active state. The control line may be configured to have or trend toward the first voltage when the bus is in the idle state.

公开(公告)号：US20240256187A1

公开(公告)日：2024-08-01

申请号：US18632049

申请日：2024-04-10

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Todd Jackson Plum ,  Scott D. Van De Graaff ,  Scott E. Schaefer ,  Mark D. Ingram

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679

Abstract: Methods, systems, and devices for temperature monitoring for memory devices are described for monitoring one or more temperature ranges experienced by a memory device. The memory device may include monitoring circuitry or logic that may identify one or more durations of operating the memory device within the one or more temperature ranges. The memory device may store an indication of the one or more durations, or an indication of information associated with the one or more durations. The indication may be accessed a host device associated with the memory device or may be transmitted by the memory device to the host device. The host device may use information included in the indication to perform an operation associated with the memory device.

公开(公告)号：US12038806B2

公开(公告)日：2024-07-16

申请号：US17807813

申请日：2022-06-20

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm ,  Scott D. Van De Graaff ,  Mark D. Ingram ,  Todd Jackson Plum

IPC: G11C29/00 ,  G06F9/30 ,  G06F11/07 ,  G06F11/10 ,  G06F11/30

CPC classification number: G06F11/1068 ,  G06F9/30189 ,  G06F11/0772 ,  G06F11/3051

Abstract: Methods, systems, and devices for evaluation of memory device health monitoring logic are described. For example, a memory device may include health monitoring logic operable to activate certain internal health monitors of a set of multiple monitors and to communicate an output associated with the activated monitors. In a first mode of operation, the health monitoring logic may provide a single output that is generated from multiple outputs of the set of monitors. In a second mode of operation, the health monitoring logic may cycle through certain monitors (e.g., in a test mode), and may generate an output corresponding to respective active monitors as it cycles through the set of monitors. The health monitoring logic may communicate an output specific to each monitor to a host device such that the host device may evaluate an output from each monitor of the set of monitors.

公开(公告)号：US11990200B2

公开(公告)日：2024-05-21

申请号：US17580329

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/18 ,  G11C29/42

CPC classification number: G11C29/4401 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/42 ,  G11C2029/1806

Abstract: Methods, systems, and devices for bit retiring to mitigate bit errors are described. A memory device may retrieve a set of bits from a first row of an address space and may determine that the set of bits includes one or more errors. The memory device may remap at least a portion of the first row from a first row index to a second row index, where the second row index, before the remapping, corresponds to a second row within the address space addressable by the host device. Additionally or alternatively, the memory device may receive a first command to access a first logical address of a memory array that is associated with a first row index. The memory device may determine that the first row includes one or more errors and may transmit a signal indicating that the first row includes the one or more errors.