-
公开(公告)号：US20240004807A1
公开(公告)日：2024-01-04
申请号：US18215434
申请日：2023-06-28
Applicant: Micron Technology, Inc.
Inventor： Paolo Amato , Marco Sforzin , Stephen S. Pawlowski
IPC: G06F13/16
CPC classification number: G06F13/161
Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The memory system with such memory units implemented can still provide a degree of data integrity and/or data authenticity required by standardized requirements and/or protocols, such as trusted execution engine security protocol (TSP).
-
公开(公告)号：US20240004759A1
公开(公告)日：2024-01-04
申请号：US18215588
申请日：2023-06-28
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato
IPC: G06F11/10
CPC classification number: G06F11/1076
Abstract: Data protection with error correction/detection capabilities can be provided on a cache line basis. When provided on a cache line basis to collectively protect the cache line data, the error correction/detection capabilities can be provided with fewer number of bits (e.g., error correction code (ECC) and/or cyclic redundancy check (CRC) bits) as compared to providing the same error correction/detection capabilities individually on a subset of the cache line data.
-
公开(公告)号：US20240004756A1
公开(公告)日：2024-01-04
申请号：US18211881
申请日：2023-06-20
Applicant: Micron technology, Inc.
Inventor： Joseph M. McCrate , Marco Sforzin , Paolo Amato , Lingming Yang , Nevil N. Gajera
CPC classification number: G06F11/1068 , G06F11/0772
Abstract: Methods, systems, and devices for data correction schemes with reduced device overhead are described. A memory system may include a set of memory devices storing data and check codes associated with the data. The memory system may additionally include a single parity device storing parity information associated with the data. During a read operation of a set of data, a controller of the memory system may detect an error in data associated with a first check code, the data including two or more subsets of the set of data received from two or more corresponding memory devices. The controller may generate candidate data corresponding to one of the two or more subsets using the parity information and remaining subsets of the set of data. Then the controller may determine whether the candidate data is correct by comparing the first check code with a check value generated using the candidate data.
-
公开(公告)号：US20230393940A1
公开(公告)日：2023-12-07
申请号：US17831433
申请日：2022-06-02
Applicant: Micron Technology, Inc.
Inventor： Nicola Del Gatto , Marco Sforzin , Paolo Amato
IPC: G06F11/10
CPC classification number: G06F11/1096
Abstract: One or more data blocks of a write command can be written to memory devices independently of other data blocks that are grouped together for an error correction operation with the data blocks. Further, data blocks of different write commands can be executed together and simultaneously rather than being executed separately at different times, which can reduce the latencies associated with executing the write commands.
-
公开(公告)号：US11721395B2
公开(公告)日：2023-08-08
申请号：US17518176
申请日：2021-11-03
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Daniele Balluchi
Abstract: Methods, systems, and devices for timing parameter adjustment mechanisms are described. The memory system may receive an access command to access a block of data. Based on receiving the access command, the memory system may determine a parameter (e.g., a timing parameter) associated with accessing the block of data. The timing parameter may indicate a duration between a first time to access a first page of the block of data and a second time to access a second page of the block of data. The memory system may perform an access operation on the block of data based on determining the timing parameter.
-
Patent Agency Ranking
公开(公告)号：US20230214119A1
公开(公告)日：2023-07-06
申请号：US17955907
申请日：2022-09-29
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Daniele Balluchi
CPC classification number: G06F3/061 , G06F3/0629 , G06F3/0673 , G06F11/1004
Abstract: Systems, apparatuses, and methods related to data stripe protection are described. An error management component can process multiple read/write/recovery requests concurrently. When read/write requests are to be processed on respective strips of a stripe, the error management component can process (e.g., concurrently) the read/write requests to determine a quantity of errors within each one of the strips and the determined quantity can be used to further determine whether to access other memory portions to correct the determined quantity.
-
公开(公告)号：US20230005563A1
公开(公告)日：2023-01-05
申请号：US17366988
申请日：2021-07-02
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin
Abstract: The present disclosure includes apparatuses, methods, and systems for programming codewords for error correction operations to memory. An embodiment includes a memory having a plurality of groups of memory cells, wherein each respective one of the plurality of groups includes a plurality of sub-groups of memory cells, and circuitry configured to program a portion of a codeword for an error correction operation to one of the plurality of groups of memory cells by determining an address in that group of memory cells by performing an XOR operation on an address of one of the plurality of sub-groups of that group of memory cells, and programming the portion of the codeword to the determined address.
-
公开(公告)号：US20220261363A1
公开(公告)日：2022-08-18
申请号：US17673731
申请日：2022-02-16
Applicant: Micron Technology, Inc.
Inventor： Emanuele Confalonieri , Daniele Balluchi , Paolo Amato , Danilo Caraccio , Marco Sforzin
IPC: G06F13/16
Abstract: Systems, apparatuses, and methods related to a controller for managing multiple types of memory are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit can manage a first type of memory device that operates according to a first set of timing characteristics and a second type of memory device that operates according to a second set of timing characteristics. The central controller portion is configured to cause performance of a memory operation and comprises a cache memory to buffer data associated performance of the memory operation, a security component configured to encrypt the data before storing the data in the first type of memory device or the second type of memory device, and error correction code (ECC) circuitry to ECC encode and ECC decode the data.
-
公开(公告)号：US20220246220A1
公开(公告)日：2022-08-04
申请号：US17726351
申请日：2022-04-21
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Umberto Di Vincenszo , Daniele Balluchi
Abstract: Methods, systems, and devices for operational modes for reduced power consumption in a memory system are described. A memory device may be coupled with a capacitor of a power management integrated circuit (PMIC). The memory device may operate in a first mode where a supply voltage is provided to the memory device from the PMIC. The memory device may operate in a second mode where it is isolated from the PMIC. When isolated, a node of the memory device (e.g., an internal node) may be discharged while the capacitor of the PMIC remains charged. When the memory device resumes operating in the first mode, a supply voltage may be provided to it based on the residual charge of the capacitor.
-
公开(公告)号：US20220223204A1
公开(公告)日：2022-07-14
申请号：US17707116
申请日：2022-03-29
Applicant: Micron Technology, Inc.
Inventor： Paolo Amato , Marco Sforzin
IPC: G11C13/00
Abstract: The present disclosure relates to a memory device comprising a plurality of memory cells, each memory cell being programmable to a logic state corresponding to a threshold voltage exhibited by the memory cell in response to an applied voltage, and a logic circuit portion operatively coupled to the plurality of memory cells, wherein the logic circuit portion is configured to scan memory addresses of the memory device, and to generate seasoning pulses to be applied to the addressed pages of the memory device. A related electronic system and related methods are also disclosed.
-
-
-
-
-
-
-
-
-
Search Results
216
records
(took 0.022 seconds)
