公开(公告)号：US08068614B2

公开(公告)日：2011-11-29

申请号：US11864887

申请日：2007-09-28

Applicant: Mohan J. Kumar ,  Shay Gueron

Inventor： Mohan J. Kumar ,  Shay Gueron

IPC: H04L9/08 ,  G06F3/00 ,  H04L9/32

CPC classification number: G06F21/572 ,  G06F21/575

Abstract: A processing system may include a processing unit and nonvolatile storage responsive to the processing unit. The nonvolatile storage may include a candidate boot code module and an authentication code module. The processing unit may be configured to execute code from the authentication code module before executing code from the candidate boot code module. The authentication code module may have instructions which, when executed by the processing unit, cause the processing unit to read a processor identifier from the processing unit and determine whether the processor belongs to a predetermined set of processors associated with a specific vendor, based at least in part on the identifier, before executing any instructions from the candidate boot code module. The processing system may also test authenticity of the candidate boot code module before executing any instructions from the candidate boot code module. Other embodiments are described and claimed.

Abstract translation: 处理系统可以包括响应于处理单元的处理单元和非易失性存储器。 非易失性存储器可以包括候选引导代码模块和认证代码模块。 处理单元可以被配置为在从候选引导代码模块执行代码之前从认证代码模块执行代码。 认证代码模块可以具有指令，当由处理单元执行时，处理单元至少从处理单元读取处理器标识符并且确定处理器是否属于与特定供应商相关联的预定处理器集合 部分地在标识符上，在执行来自候选引导代码模块的任何指令之前。 在执行来自候选引导代码模块的任何指令之前，处理系统还可以测试候选引导代码模块的真实性。 描述和要求保护其他实施例。

公开(公告)号：US07971048B2

公开(公告)日：2011-06-28

申请号：US12056452

申请日：2008-03-27

Applicant: Sham M. Datta ,  Mohan J. Kumar ,  Ernest Brickell

Inventor： Sham M. Datta ,  Mohan J. Kumar ,  Ernest Brickell

IPC: G06F15/177

CPC classification number: G06F21/57

Abstract: Embodiments of the invention provide systems and methods associated with a measurement engine in a server platform. In one such embodiment of the invention, the measurement engine hardware verifies/authenticates its own firmware and then system initialization firmware by measuring such firmware and storing measurement results in a register that is not spoofable by malicious code. In this instance, the measurement engine holds the host CPU complex in a reset state until the measurement engine has verified the system initialization firmware. In another such embodiment of the invention, the measurement engine hardware also measures firmware associated with one or more system service processors and stores such measurement results in a register. In this case, the measurement engine holds the system service processors and the host CPU complex in reset until the measurements are completed. Other embodiments are described.

Abstract translation: 本发明的实施例提供了与服务器平台中的测量引擎相关联的系统和方法。 在本发明的一个这样的实施例中，测量引擎硬件通过测量这样的固件来验证/认证其自己的固件，然后验证其自身的固件，并将测量结果存储在恶意代码不能欺骗的寄存器中。 在这种情况下，测量引擎将主机复合体保持在复位状态，直到测量引擎已经验证了系统初始化固件。 在本发明的另一个这样的实施例中，测量引擎硬件还测量与一个或多个系统服务处理器相关联的固件并将这样的测量结果存储在寄存器中。 在这种情况下，测量引擎将系统服务处理器和主机CPU复合体保持在复位状态，直到测量完成。 描述其他实施例。

公开(公告)号：US07546487B2

公开(公告)日：2009-06-09

申请号：US11227831

申请日：2005-09-15

Applicant: Suresh Marisetty ,  Andrew J. Fish ,  Koichi Yamada ,  Scott D. Brenden ,  James B. Crossland ,  Shivnandan Kaushik ,  Mohan J. Kumar ,  Jose A. Vargas

Inventor： Suresh Marisetty ,  Andrew J. Fish ,  Koichi Yamada ,  Scott D. Brenden ,  James B. Crossland ,  Shivnandan Kaushik ,  Mohan J. Kumar ,  Jose A. Vargas

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0706

Abstract: Methods and architectures for performing hardware error handling using coordinated operating system (OS) and firmware services. In one aspect, a firmware interface is provided to enable an OS to access firmware error-handling services. Such services enable the OS to access error data concerning platform hardware errors that may not be directed accessed via a platform processor or through other conventional approaches. Techniques are also disclosed for intercepting the processing of hardware error events and directing control to firmware error-handling services prior to attempting to service the error using OS-based services. The firmware services may correct hardware errors and/or log error data that may be later accessed by the OS or provided to a remote management server using an out-of-band communication channel. In accordance with another aspect, the firmware intercept and services may be performed in a manner that is transparent to the OS.

Abstract translation: 使用协调操作系统（OS）和固件服务执行硬件错误处理的方法和架构。 在一个方面，提供固件接口以使OS能够访问固件错误处理服务。 这样的服务使得OS能够访问有关平台硬件错误的错误数据，这些错误数据可能不会通过平台处理器或其他常规方法被定向访问。 还公开了用于在使用基于OS的服务尝试服务错误之前拦截硬件错误事件的处理以及将控制引导到固件错误处理服务的技术。 固件服务可以纠正OS稍后访问或使用带外通信信道提供给远程管理服务器的硬件错误和/或日志错误数据。 根据另一方面，固件拦截和服务可以以对OS是透明的方式来执行。

公开(公告)号：US07437643B2

公开(公告)日：2008-10-14

申请号：US11157526

申请日：2005-06-21

Applicant: Rahul Khanna ,  Mohan J. Kumar ,  Jay Nejedlo

Inventor： Rahul Khanna ,  Mohan J. Kumar ,  Jay Nejedlo

IPC: G01R31/28

CPC classification number: G06F11/27

Abstract: Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is posted, wherein the link status is based at least in part on the result from the link training and the result from the BIST.

Abstract translation: 执行链接的训练，其中链路是计算机系统的两个设备之间的互连。 链接的内置自检（BIST）被执行。 将链接训练的结果与BIST的结果进行比较。 张贴链接的链接状态，其中链接状态至少部分地基于链接训练的结果和来自BIST的结果。

公开(公告)号：US20080163331A1

公开(公告)日：2008-07-03

申请号：US11618649

申请日：2006-12-29

Applicant: Sham M. Datta ,  Mohan J. Kumar ,  James A. Sutton ,  Ernie Brickell ,  Ioannis T. Schoinas

Inventor： Sham M. Datta ,  Mohan J. Kumar ,  James A. Sutton ,  Ernie Brickell ,  Ioannis T. Schoinas

IPC: G06F21/00 ,  G06F17/00

CPC classification number: G06F21/57

Abstract: Apparatuses, methods, and systems for reconfiguring a secure system are disclosed. In one embodiment, an apparatus includes a configuration storage location, a lock, and lock override logic. The configuration storage location is to store information to configure the apparatus. The lock is to prevent writes to the configuration storage location. The lock override logic is to allow instructions executed from sub-operating mode code to override the lock.

Abstract translation: 公开了用于重新配置安全系统的装置，方法和系统。 在一个实施例中，装置包括配置存储位置，锁定和锁定超驰逻辑。 配置存储位置是存储信息以配置设备。 该锁是为了防止写入配置存储位置。 锁定覆盖逻辑是允许从子操作模式代码执行的指令覆盖锁定。

公开(公告)号：US6065123A

公开(公告)日：2000-05-16

申请号：US978545

申请日：1997-11-26

Applicant: Stephen T. Chou ,  Russell J. Fenger ,  Mohan J. Kumar ,  Victor B. Lortz ,  Benjamin L. Manny ,  Mil Travnicek ,  Chih-Kan Wang

Inventor： Stephen T. Chou ,  Russell J. Fenger ,  Mohan J. Kumar ,  Victor B. Lortz ,  Benjamin L. Manny ,  Mil Travnicek ,  Chih-Kan Wang

IPC: G06F1/32 ,  G06F11/14 ,  G06F9/00

CPC classification number: G06F1/3265 ,  G06F1/3203 ,  G06F1/3209 ,  G06F11/1441 ,  Y02B60/1242

Abstract: A computer system with unattended on-demand availability includes power-saving features which place the system into a Standby mode whenever the system is idle or is not being used. Prior to entering Standby mode, the system sets a hardware timer which indicates when the next scheduled event in the system should be performed. When either the timer expires or another event occurs which requires system operation, the system resumes to the On power state without user intervention. In one embodiment, the system of the present invention allows applications to periodically save their operational states. By saving their operational states, applications are able to guard against power failures and crashes. If a power failure or crash occurs, the system consults restart policies and, if appropriate, automatically re-starts applications to their most recently saved operational states once power is re-stored.

Abstract translation: 具有无人值守按需可用性的计算机系统包括省电功能，当系统空闲或未使用时，系统进入待机模式。 在进入待机模式之前，系统设置一个硬件定时器，指示系统中下次调度的事件何时执行。 当定时器超时或需要系统操作的另一个事件时，系统将恢复到On电源状态，无需用户干预。 在一个实施例中，本发明的系统允许应用程序周期性地保存其操作状态。 通过保存操作状态，应用程序能够防止电源故障和崩溃。 如果发生电源故障或发生故障，系统将重新启动策略，并在适当的情况下自动将应用程序重新启动到其最近保存的操作状态，一旦重新存储电源。

公开(公告)号：US5902352A

公开(公告)日：1999-05-11

申请号：US909384

申请日：1997-08-11

Applicant: Stephen T. Chou ,  Russell J. Fenger ,  Mohan J. Kumar ,  Victor B. Lortz ,  Mil Travnicek ,  Chih-Kan Wang

Inventor： Stephen T. Chou ,  Russell J. Fenger ,  Mohan J. Kumar ,  Victor B. Lortz ,  Mil Travnicek ,  Chih-Kan Wang

IPC: G06F9/48 ,  G06F9/00

CPC classification number: G06F9/4881

Abstract: A method and apparatus for task scheduling across multiple execution sessions allows each scheduled task to be scheduled to occur at a specific time(s), to occur periodically, or to occur in response to certain system events. A task can be scheduled which requires execution of an application even if the application is not running at the scheduled time or event, and even if the system is in a low-power standby mode at the scheduled time or event. In one embodiment, the present invention keeps track of specific time events by setting a timer(s) which indicates the time which should elapse until a scheduled event is to occur. When a timer expires, the system determines which task is scheduled to occur at the time the timer expires and executes that task. In one embodiment, the present invention checks a scheduling database to determine which task is scheduled to occur when a timer expires.

Abstract translation: 用于跨越多个执行会话的任务调度的方法和装置允许调度每个调度的任务在特定时间发生，周期性地发生，或者响应于某些系统事件而发生。 即使应用程序未在预定的时间或事件中运行，并且即使系统在预定时间或事件中处于低功耗待机模式，也可以调度任务，该任务需要执行应用程序。 在一个实施例中，本发明通过设置指示应该经过的时间的定时器来跟踪特定的时间事件，直到发生调度的事件。 当定时器到期时，系统确定在定时器到期时调度哪个任务发生，并执行该任务。 在一个实施例中，本发明检查调度数据库以确定当定时器到期时调度哪个任务发生。

公开(公告)号：US10331614B2

公开(公告)日：2019-06-25

申请号：US15025988

申请日：2013-11-27

Applicant: INTEL CORPORATION ,  Dimitrios Ziakas ,  Bassam N. Coury ,  Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Thi Dang ,  Russell J. Wunderlich

Inventor： Dimitrios Ziakas ,  Bassam N. Coury ,  Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Thi Dang ,  Russell J. Wunderlich

IPC: G06F11/00 ,  G06F15/78 ,  G06F11/10 ,  G06F11/34 ,  G06F11/16

Abstract: Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.

公开(公告)号：US20180034909A1

公开(公告)日：2018-02-01

申请号：US15221707

申请日：2016-07-28

Applicant: Murugasamy K. Nachimuthu ,  Mohan J. Kumar

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar

IPC: H04L29/08 ,  H04L12/24

Abstract: Mechanisms for efficient discovery of storage resources in a Rack Scale Architecture (RSA) system and associated methods, apparatus, and systems. A rack is populated with pooled system drawers including pooled compute drawers and pooled storage drawers communicatively coupled via input-output (IO) cables. Compute nodes including one or more processors, memory resources, and optional local storage resources are installed in the pooled compute drawers, and are enabled to be selectively-coupled to storage resources in the pooled storage drawers over virtual attachment links. During a discovery process, a compute node determines storage resource characteristics of storage resources it may be selectively-coupled to and the attachment links used to access the storage resources. The storage resource characteristics are aggregated by a pod manager that uses corresponding configuration information to dynamically compose compute nodes for rack users based on user needs.

公开(公告)号：US09600416B2

公开(公告)日：2017-03-21

申请号：US13997189

申请日：2011-09-30

Applicant: Raj K. Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn J. Hinton

Inventor： Raj K. Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn J. Hinton

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/08 ,  G11C11/406 ,  G11C14/00

CPC classification number: G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/2024 ,  G06F2212/205 ,  G11C11/40615 ,  G11C14/009 ,  Y02D10/13

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”