公开(公告)号：US09953455B2

公开(公告)日：2018-04-24

申请号：US13802182

申请日：2013-03-13

Applicant: NVIDIA CORPORATION

Inventor： Eric B. Lum ,  Rui Bastos ,  Jerome F. Duluk, Jr. ,  Henry Packard Moreton ,  Yury Y. Uralsky

IPC: G06T15/00 ,  G06T15/40

CPC classification number: G06T15/00 ,  G06T15/005 ,  G06T15/405

Abstract: Techniques are disclosed for storing post-z coverage data in a render target. A color raster operations (CROP) unit receives a coverage mask associated with a portion of a graphics primitive, where the graphics primitive intersects a pixel that includes a multiple samples, and the portion covers at least one sample. The CROP unit stores the coverage mask in a data field in the render target at a location associated with the pixel. One advantage of the disclosed techniques is that the GPU computes color and other pixel information only for visible fragments as determined by post-z coverage data. The GPU does not compute color and other pixel information for obscured fragments, thereby reducing overall power consumption and improving overall render performance.

公开(公告)号：US09798487B2

公开(公告)日：2017-10-24

申请号：US15243909

申请日：2016-08-22

Applicant: NVIDIA Corporation

Inventor： Jerome F. Duluk, Jr. ,  Cameron Buschardt ,  James Leroy Deming ,  Lucien Dunning ,  Brian Fahs ,  Mark Hairgrove ,  Chenghuan Jia ,  John Mashey ,  James M. Van Dyke

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/122

CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0683 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/122 ,  G06F2212/652

Abstract: One embodiment of the present invention sets forth a computer-implemented method for migrating a memory page from a first memory to a second memory. The method includes determining a first page size supported by the first memory. The method also includes determining a second page size supported by the second memory. The method further includes determining a use history of the memory page based on an entry in a page state directory associated with the memory page. The method also includes migrating the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history.

公开(公告)号：US09792220B2

公开(公告)日：2017-10-17

申请号：US14011655

申请日：2013-08-27

Applicant: NVIDIA CORPORATION

Inventor： Cameron Buschardt ,  Jerome F. Duluk, Jr. ,  John Mashey ,  Mark Hairgrove ,  James Leroy Deming ,  Brian Fahs

IPC: G06F12/00 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/301

Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

公开(公告)号：US09355041B2

公开(公告)日：2016-05-31

申请号：US14105015

申请日：2013-12-12

Applicant: NVIDIA CORPORATION

Inventor： John Mashey ,  Cameron Buschardt ,  James Leroy Deming ,  Jerome F. Duluk, Jr. ,  Brian Fahs

IPC: G06F12/10

CPC classification number: G06F3/0622 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/656 ,  G06F2212/684

Abstract: One embodiment of the present invention is a memory subsystem that includes a sliding window tracker that tracks memory accesses associated with a sliding window of memory page groups. When the sliding window tracker detects an access operation associated with a memory page group within the sliding window, the sliding window tracker sets a reference bit that is associated with the memory page group and is included in a reference vector that represents accesses to the memory page groups within the sliding window. Based on the values of the reference bits, the sliding window tracker causes the selection a memory page in a memory page group that has fallen into disuse from a first memory to a second memory. Because the sliding window tracker tunes the memory pages that are resident in the first memory to reflect memory access patterns, the overall performance of the memory subsystem is improved.

Abstract translation: 本发明的一个实施例是一种存储器子系统，其包括跟踪与存储器页组的滑动窗口相关联的存储器访问的滑动窗口跟踪器。 当滑动窗口跟踪器检测到与滑动窗口内的存储器页面组相关联的访问操作时，滑动窗口跟踪器设置与存储器页面组相关联的参考位，并且被包括在表示对存储器页面的访问的参考向量中 在滑动窗口内的组。 基于参考位的值，滑动窗口跟踪器使选择已经从第一存储器废弃到第二存储器的存储器页组中的存储器页。 因为滑动窗口跟踪器调谐驻留在第一存储器中的存储器页面以反映存储器访问模式，所以提高了存储器子系统的整体性能。

公开(公告)号：US09183609B2

公开(公告)日：2015-11-10

申请号：US13723092

申请日：2012-12-20

Applicant: NVIDIA CORPORATION

Inventor： Rui Bastos ,  Mark J. Kilgard ,  William Craig McKnight ,  Jerome F. Duluk, Jr. ,  Pierre Souillot ,  Dale L. Kirkland ,  Christian Amsinck ,  Joseph Detmer ,  Christian Rouet ,  Don Bittel

IPC: G09G5/00 ,  G06T1/20 ,  G06T15/50 ,  G06T11/40

CPC classification number: G06T1/20 ,  G06T11/40 ,  G06T15/503 ,  G09G2340/10

Abstract: A technique for efficiently rendering content reduces each complex blend mode to a series of basic blend operations. The series of basic blend operations are executed within a recirculating pipeline until a final blended value is computed. The recirculating pipeline is positioned within a color raster operations unit of a graphics processing unit for efficient access to image buffer data.

Abstract translation: 用于有效地呈现内容的技术将每个复合混合模式减少到一系列基本的混合操作。 一系列基本混合操作在循环管线内执行，直到计算最终混合值。 再循环管线位于图形处理单元的彩色光栅操作单元内，用于有效地访问图像缓冲器数据。

公开(公告)号：US09098925B2

公开(公告)日：2015-08-04

申请号：US13942447

申请日：2013-07-15

Applicant: NVIDIA CORPORATION

Inventor： Eric B. Lum ,  Jerome F. Duluk, Jr.

IPC: G06F12/02 ,  G06T1/60

CPC classification number: G06T1/60 ,  G06T11/40 ,  G06T15/005

Abstract: One embodiment sets forth a method for associating each stencil value included in a stencil buffer with multiple fragments. Components within a graphics processing pipeline use a set of stencil masks to partition the bits of each stencil value. Each stencil mask selects a different subset of bits, and each fragment is strategically associated with both a stencil value and a stencil mask. Before performing stencil actions associated with a fragment, the raster operations unit performs stencil mask operations on the operands. No fragments are associated with both the same stencil mask and the same stencil value. Consequently, no fragments are associated with the same stencil bits included in the stencil buffer. Advantageously, by reducing the number of stencil bits associated with each fragment, certain classes of software applications may reduce the wasted memory associated with stencil buffers in which each stencil value is associated with a single fragment.

Abstract translation: 一个实施例提出了一种用于将包括在模板缓冲器中的每个模版值与多个片段相关联的方法。 图形处理流水线中的组件使用一组模板掩模来分割每个模板值的位。 每个模板掩模选择不同的位子集，并且每个片段与模板值和模板掩模两者战略性地相关联。 在执行与片段相关联的模板操作之前，光栅操作单元对操作数执行模板掩码操作。 没有碎片与相同的模板掩模和相同的模板值相关联。 因此，没有碎片与包括在模板缓冲器中的相同模板位相关联。 有利地，通过减少与每个片段相关联的模板位的数量，某些类别的软件应用可以减少与模板缓冲器相关联的浪费的存储器，其中每个模板值与单个片段相关联。

公开(公告)号：US20140337569A1

公开(公告)日：2014-11-13

申请号：US13890178

申请日：2013-05-08

Applicant: NVIDIA CORPORATION

Inventor： Scott Ricketts ,  Brian Scott Pharris ,  Nicholas Wang ,  Luke David Durant ,  Philip Alexander Cuadra ,  Jerome F. Duluk, Jr.

IPC: G06F12/08 ,  G11C11/406

CPC classification number: G06F12/0804 ,  G06F9/4843 ,  G06F12/0802

Abstract: A system, method, and computer program product for low-latency scheduling and launch of memory defined tasks. The method includes the steps of receiving a task metadata data structure to be stored in a memory associated with a processor, transmitting the task metadata data structure to a scheduling unit of the processor, storing the task metadata data structure in a cache unit included in the scheduling unit, and copying the task metadata data structure from the cache unit to the memory.

Abstract translation: 一种用于低延迟调度和启动内存定义任务的系统，方法和计算机程序产品。 该方法包括以下步骤：接收要存储在与处理器相关联的存储器中的任务元数据数据结构，将任务元数据结构发送到处理器的调度单元，将任务元数据结构存储在包括在该处理器中的高速缓存单元中 调度单元，以及将任务元数据结构从高速缓存单元复制到存储器。