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    Prioritized Memory Reads
    1.
    发明申请
    Prioritized Memory Reads 审中-公开
    优先级内存读取

    公开(公告)号：US20150193358A1

    公开(公告)日：2015-07-09

    申请号：US14148277

    申请日：2014-01-06

    Applicant: NVIDIA Corporation

    Inventor： James M. Van Dyke ,  Robert Ohannessian, JR.

    IPC: G06F13/16 ,  G06F13/18 ,  G06F12/08

    CPC classification number: G06F13/161 ,  G06F8/4441 ,  G06F9/3824 ,  G06F9/3836 ,  G06F12/0875 ,  G06F13/1626 ,  G06F13/18 ,  G06F2212/452 ,  G06F2212/6026

    Abstract: A system includes a processing unit and a memory system coupled to the processing unit. The processing unit is configured to mark a memory access in the series of instructions as a priority memory access as a consequence of the memory access having a dependent instruction following less than a threshold distance after the memory access in the series of instructions. The processing unit is configured to send the marked memory access to the memory system.

    Abstract translation: 系统包括处理单元和耦合到处理单元的存储器系统。 所述处理单元被配置为将所述一系列指令中的存储器访问标记为优先级存储器访问，作为所述存储器访问的结果，所述存储器访问具有在所述一系列指令中的存储器访问之后小于阈值距离的依赖指令。 处理单元被配置为将标记的存储器访问发送到存储器系统。

    TECHNIQUES FOR EFFICIENTLY PARTITIONING MEMORY
    2.
    发明申请
    TECHNIQUES FOR EFFICIENTLY PARTITIONING MEMORY 有权

    公开(公告)号：US20210049097A1

    公开(公告)日：2021-02-18

    申请号：US16541417

    申请日：2019-08-15

    Applicant: NVIDIA Corporation

    Inventor： Kun Fang ,  James M. Van Dyke

    IPC: G06F12/06 ,  G06F3/06

    Abstract: Techniques are disclosed for allocating a global memory space defined within physical memory devices into strided memory space(s) (SMS) and partition memory space(s) (PMS). In an embodiment, a SMS is mapped across all of the devices, and a PMS is mapped to a subset of the devices to ensure resource isolation between separate PMSs. Typically, a memory space is allocated in unit sizes. When the locations mapped to most of the SMS align to an integer number of the unit size, a common boundary can be formed between the SMS and the one or more PMSs in each of the devices. Such a boundary can advantageously minimize a region of locations that are not available for allocation in the global memory spaces. In an embodiment, when a strided allocation is not an integer number of the unit size, a remainder is mapped to locations for one or more PMSs.

    Techniques for efficiently partitioning memory
    5.
    发明授权
    Techniques for efficiently partitioning memory 有权

    公开(公告)号：US10909033B1

    公开(公告)日：2021-02-02

    申请号：US16541417

    申请日：2019-08-15

    Applicant: NVIDIA Corporation

    Inventor： Kun Fang ,  James M. Van Dyke

    IPC: G06F12/00 ,  G06F12/06 ,  G06F3/06

    Abstract: Techniques are disclosed for allocating a global memory space defined within physical memory devices into strided memory space(s) (SMS) and partition memory space(s) (PMS). In an embodiment, a SMS is mapped across all of the devices, and a PMS is mapped to a subset of the devices to ensure resource isolation between separate PMSs. Typically, a memory space is allocated in unit sizes. When the locations mapped to most of the SMS align to an integer number of the unit size, a common boundary can be formed between the SMS and the one or more PMSs in each of the devices. Such a boundary can advantageously minimize a region of locations that are not available for allocation in the global memory spaces. In an embodiment, when a strided allocation is not an integer number of the unit size, a remainder is mapped to locations for one or more PMSs.

    Selecting hash values based on matrix rank
    7.
    发明授权
    Selecting hash values based on matrix rank 有权

    公开(公告)号：US09690715B2

    公开(公告)日：2017-06-27

    申请号：US14475951

    申请日：2014-09-03

    Applicant: NVIDIA CORPORATION

    Inventor： James M. Van Dyke

    IPC: G06F12/08 ,  G06F12/1018 ,  G06F12/0875 ,  G06F12/02 ,  G06F12/0864 ,  G06F12/14

    CPC classification number: G06F12/1018 ,  G06F12/0207 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/1408 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/455 ,  G06F2212/601 ,  G06F2212/651

    Abstract: One embodiment of the present invention includes a hash selector that facilitates performing effective hashing operations. In operation, the hash selector creates a transformation matrix that reflects specific optimization criteria. For each hash value, the hash selector generates a potential hash value and then computes the rank of a submatrix included in the transformation matrix. Based on this rank in conjunction with the optimization criteria, the hash selector either re-generates the potential hash value or accepts the potential hash value. Advantageously, the optimization criteria may be tailored to create desired correlations between input patterns and the results of performing hashing operations based on the transformation matrix. Notably, the hash selector may be configured to efficiently and reliably incrementally generate a transformation matrix that, when applied to certain strides of memory addresses, produces a more uniform distribution of accesses across caches lines than previous approaches to memory addressing.

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