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    Semiconductor memory device
    51.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US08315094B2

    公开(公告)日：2012-11-20

    申请号：US12957865

    申请日：2010-12-01

    申请人： Kazushige Kanda ,  Toshiki Hisada ,  Katsuaki Isobe

    发明人： Kazushige Kanda ,  Toshiki Hisada ,  Katsuaki Isobe

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

    摘要： Provided is a semiconductor memory device including: multiple bit lines arranged in parallel to one another; multiple sense-amplifier bit lines arranged away from end portions of the bit lines; a fourth sense-amplifier bit line formed with a wire of a first layer arranged below the bit lines; selection transistors with a pair of gate electrodes arranged in a direction normal to the first to sixth bit lines; a first wire arranged below the bit lines and the sense-amplifier bit lines, and having an end portion extending to below the third bit line and connected to the bit line; a third wire formed with a layer of the gate electrode used as a wire, the third wire including a first end portion positioned below the fourth sense-amplifier bit line and connected to the fourth sense-amplifier bit line, and a second end portion positioned below the second sense-amplifier bit line; and a fourth wire formed with a wire of the first layer and arranged between the third wire and the second sense-amplifier bit line to connect the third wire to the second sense-amplifier bit line.

    摘要翻译： 提供一种半导体存储器件，包括：彼此平行布置的多个位线; 多个读出放大器位线布置成远离位线的端部; 第四感测放大器位线，其布置在位线下方的第一层的导线; 选择晶体管，其具有沿与第一至第六位线垂直的方向排列的一对栅电极; 布置在位线下方的第一线和读出放大器位线，并且具有延伸到第三位线下方并连接到位线的端部; 第三线，其形成有用作线的栅极电极层，所述第三线包括位于所述第四感测放大器位线下方并连接到所述第四感测放大器位线的第一端部，以及位于 低于第二感测放大器位线; 以及第四导线，其由第一层的导线形成，并且布置在第三导线和第二读出放大器位线之间，以将第三导线连接到第二感测放大器位线。

    Semiconductor memory device and inspecting method of the same
    52.
    发明授权
    Semiconductor memory device and inspecting method of the same 失效
    半导体存储器件及其检测方法

    公开(公告)号：US08149638B2

    公开(公告)日：2012-04-03

    申请号：US12884694

    申请日：2010-09-17

    申请人： Tomonori Kurosawa ,  Takahiko Sasaki ,  Kazushige Kanda

    发明人： Tomonori Kurosawa ,  Takahiko Sasaki ,  Kazushige Kanda

    IPC分类号： G11C7/00

    CPC分类号： G11C29/02 ,  G11C11/16 ,  G11C29/025 ,  G11C2029/1204

    摘要： According to one embodiment, a semiconductor memory device includes a memory cell array includes memory cells, lines provided to correspond to the memory cells, a first decoder configured to select a first line as an inspection target from the lines, a second decoder configured to select a second line for generating a reference voltage from the lines, a driver configured to charge the first and second lines, a discharging circuit configured to simultaneously discharge the first and second lines, and a sense amplifier configured to compare a voltage of the first line with a voltage of the second line to detect a defect of the first line while the first line is discharged.

    摘要翻译： 根据一个实施例，半导体存储器件包括存储单元阵列，其包括存储单元，提供用于对应于存储单元的线，第一解码器，被配置为从线选择第一行作为检查对象;第二解码器，被配置为选择 用于从所述线路产生参考电压的第二线路，被配置为对所述第一和第二线路充电的驱动器，配置成同时对所述第一和第二线路进行放电的放电电路;以及读出放大器，被配置为将所述第一线路的电压与 第一线的电压在第一线放电时检测第一线的缺陷。

    Semiconductor device for generating power on reset signal
    53.
    发明授权
    Semiconductor device for generating power on reset signal 失效
    用于产生上电复位信号的半导体器件

    公开(公告)号：US07646222B2

    公开(公告)日：2010-01-12

    申请号：US11376416

    申请日：2006-03-16

    申请人： Masaki Ichikawa ,  Kazushige Kanda

    发明人： Masaki Ichikawa ,  Kazushige Kanda

    IPC分类号： H03L7/00

    CPC分类号： H03K17/223 ,  G06F1/24

    摘要： A reference voltage generating circuit receives a power supply voltage and generates a reference voltage. A reference voltage level guarantee circuit generates a sense signal when the circuit senses that a value of the reference voltage has reached a predetermined value. A power supply voltage sensing circuit has a voltage comparator circuit which compares a voltage obtained by dividing a power supply voltage with the reference voltage and outputs a power ON reset signal. An operation of the voltage comparator circuit is controlled based on a sense signal. When the value of the power supply voltage increases and the value of the reference voltage reaches a predetermined value, the voltage comparator circuit operates, and a power ON reset signal is outputted in response to a result of comparison between a divisional voltage and the reference voltage.

    摘要翻译： 参考电压产生电路接收电源电压并产生参考电压。 当电路感测到参考电压的值已经达到预定值时，参考电压电平保证电路产生感测信号。 电源电压检测电路具有电压比较器电路，其将通过将电源电压分压获得的电压与参考电压进行比较，并输出电源接通复位信号。 基于感测信号来控制电压比较器电路的操作。 当电源电压值增加并且参考电压的值达到预定值时，电压比较器电路工作，并且响应于分压与参考电压之间的比较结果而输出电源复位信号 。

    Semiconductor memory device with MOS transistors each having floating gate and control gate
    54.
    发明授权
    Semiconductor memory device with MOS transistors each having floating gate and control gate 失效
    具有MOS晶体管的半导体存储器件分别具有浮动栅极和控制栅极

    公开(公告)号：US07428161B2

    公开(公告)日：2008-09-23

    申请号：US11537880

    申请日：2006-10-02

    申请人： Kazushige Kanda

    发明人： Kazushige Kanda

    IPC分类号： G11C5/06 ,  G11C11/34 ,  G11C16/04 ,  G11C8/00

    CPC分类号： G11C5/063 ,  G06F11/1068 ,  G11C16/24 ,  H01L27/115 ,  H01L27/11521

    摘要： A semiconductor memory device includes memory cell arrays, word lines, bit lines, column gates, sense amplifiers, and an error correcting circuit. The memory cell array includes first regions and a second region. The first region includes first element isolating regions which have stripe shapes along the bit lines. The memory cell is formed on an element region between the adjacent element isolating regions. The first regions are arranged in plurality along the word line direction. The second region is provided adjacent to the first region in a direction along the word lines. The second region includes a second element isolating region whose width along the word line direction is greater than that of the first element isolating region. Addresses of the bit line adjacent to the second region are different from one another among the memory cell arrays.

    摘要翻译： 半导体存储器件包括存储单元阵列，字线，位线，列门，读出放大器和纠错电路。 存储单元阵列包括第一区域和第二区域。 第一区域包括沿着位线具有条纹形状的第一元件隔离区域。 存储单元形成在相邻元件隔离区域之间的元件区域上。 第一区域沿字线方向排列成多个。 第二区域沿着字线的方向设置在第一区域附近。 第二区域包括其沿着字线方向的宽度大于第一元件隔离区域的宽度的第二元件隔离区域。 与第二区域相邻的位线的地址在存储单元阵列中彼此不同。

    Semiconductor device for generating power on reset signal
    57.
    发明申请
    Semiconductor device for generating power on reset signal 失效
    用于产生上电复位信号的半导体器件

    公开(公告)号：US20060208777A1

    公开(公告)日：2006-09-21

    申请号：US11376416

    申请日：2006-03-16

    申请人： Masaki Ichikawa ,  Kazushige Kanda

    发明人： Masaki Ichikawa ,  Kazushige Kanda

    IPC分类号： H03L7/00

    CPC分类号： H03K17/223 ,  G06F1/24

    摘要： A reference voltage generating circuit receives a power supply voltage and generates a reference voltage. A reference voltage level guarantee circuit generates a sense signal when the circuit senses that a value of the reference voltage has reached a predetermined value. A power supply voltage sensing circuit has a voltage comparator circuit which compares a voltage obtained by dividing a power supply voltage with the reference voltage and outputs a power ON reset signal. An operation of the voltage comparator circuit is controlled based on a sense signal. When the value of the power supply voltage increases and the value of the reference voltage reaches a predetermined value, the voltage comparator circuit operates, and a power ON reset signal is outputted in response to a result of comparison between a divisional voltage and the reference voltage.

    摘要翻译： 参考电压产生电路接收电源电压并产生参考电压。 当电路感测到参考电压的值已经达到预定值时，参考电压电平保证电路产生感测信号。 电源电压检测电路具有电压比较器电路，其将通过将电源电压分压获得的电压与参考电压进行比较，并输出电源接通复位信号。 基于感测信号来控制电压比较器电路的操作。 当电源电压值增加并且参考电压的值达到预定值时，电压比较器电路工作，并且响应于分压与参考电压之间的比较结果而输出电源复位信号 。

    Semiconductor memory device with MOS transistors each having floating gate and control gate
    58.
    发明申请
    Semiconductor memory device with MOS transistors each having floating gate and control gate 失效
    具有MOS晶体管的半导体存储器件分别具有浮动栅极和控制栅极

    公开(公告)号：US20060092724A1

    公开(公告)日：2006-05-04

    申请号：US11169633

    申请日：2005-06-30

    申请人： Kazushige Kanda

    发明人： Kazushige Kanda

    IPC分类号： G11C29/00

    CPC分类号： G11C29/846 ,  G11C8/18 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C29/808

    摘要： A semiconductor memory device includes a row address transition detector. The semiconductor memory device remedies a fault by replacing a column in a memory cell array with a redundancy bit line. The row address transition detector detects a change in a row address signal for selecting the row direction of the memory cell array. Only when a change in the row address signal is detected by the row address transition detector, the redundancy bit line is sensed.

    摘要翻译： 半导体存储器件包括行地址转换检测器。 半导体存储器件通过用冗余位线替换存储单元阵列中的列来补救故障。 行地址转换检测器检测用于选择存储单元阵列的行方向的行地址信号的变化。 只有当行地址转换检测器检测到行地址信号的变化时，才检测冗余位线。