公开(公告)号：US20140042546A1

公开(公告)日：2014-02-13

申请号：US13584156

申请日：2012-08-13

申请人： Takashi Ando ,  Min Dai ,  Martin M. Frank ,  Barry P. Linder ,  Shahab Siddiqui

发明人： Takashi Ando ,  Min Dai ,  Martin M. Frank ,  Barry P. Linder ,  Shahab Siddiqui

IPC分类号： H01L29/78 ,  H01L21/314 ,  H01L27/088

CPC分类号： H01L21/28185 ,  H01L21/02181 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518

摘要： A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.

摘要翻译： 有限数量的Hi-K材料的原子层沉积（ALD）循环，然后沉积层间电介质并施加另外的Hi-K材料并且可选但优选的退火提供了增加的Hi-K材料含量和增加的输入的击穿电压 与输入/输出（I / O）晶体管相比，与同一芯片或晶圆上形成的逻辑晶体管相比，同时提供I / O和逻辑晶体管的反型层的可扩展性，而不会明显地影响性能或偏置温度不稳定性（BTI）参数。

公开(公告)号：US08389300B2

公开(公告)日：2013-03-05

申请号：US12753270

申请日：2010-04-02

申请人： Catherine A. Dubourdieu ,  Martin M. Frank

发明人： Catherine A. Dubourdieu ,  Martin M. Frank

IPC分类号： H01L21/00

CPC分类号： H01L21/28291 ,  H01L28/55 ,  H01L29/66636 ,  H01L29/6684 ,  H01L29/7804 ,  H01L29/78391 ,  H01L29/7843 ,  H01L29/7848

摘要： A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.

摘要翻译： 控制集成电路器件部件的铁电特性的方法包括在衬底上形成铁电可控的电介质层; 以及在所述铁电可控电介质层附近形成应力施加结构，使得通过所述应力施加结构在所述铁电可控电介质层中诱发基本上单轴应变; 其中所述铁电可控介电层包括以下中的一种或多种：在没有施加应力的情况下不表现出铁电性能的铁电氧化物层和正常非铁电材料层。

公开(公告)号：US20130032886A1

公开(公告)日：2013-02-07

申请号：US13195316

申请日：2011-08-01

申请人： Takashi Ando ,  Changhwan Choi ,  Martin M. Frank ,  Unoh Kwon ,  Vijay Narayanan

发明人： Takashi Ando ,  Changhwan Choi ,  Martin M. Frank ,  Unoh Kwon ,  Vijay Narayanan

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/0922 ,  H01L21/823807 ,  H01L29/16 ,  H01L29/161 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/517

摘要： A structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in Tinv and Vt of the pFET, while scaling Tiny and maintaining Vt for the nFET, resulting in the Vt of the pFET becoming closer to the Vt of a similarly constructed nFET with scaled Tinv values.

摘要翻译： 结构具有半导体衬底以及设置在衬底上的nFET和pFET。 pFET具有形成在半导体衬底的表面上或其表面上的半导体SiGe沟道区，以及覆盖沟道区的氧化物层和覆盖氧化物层的高k电介质层的栅极电介质。 栅电极覆盖在栅极电介质上，并且具有邻接高k层的下金属层，邻接下金属层的清除金属层和与清除金属层邻接的上金属层。 金属层清除了衬底（nFET）中的氧和与氧化物层的SiGe（pFET）界面，导致pFET的Tinv和Vt有效降低，同时缩小Tiny并维持nFET的Vt，导致Vt pFET变得更接近具有缩放Tinv值的类似构造的nFET的Vt。

公开(公告)号：US20130001668A1

公开(公告)日：2013-01-03

申请号：US13550102

申请日：2012-07-16

申请人： Martin M. Frank

发明人： Martin M. Frank

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11521

摘要： A floating gate device is provided. A tunnel oxide layer is formed over the channel. A floating gate is formed over the tunnel oxide layer. A high-k dielectric layer is formed over the floating gate. A control gate is formed over the high-k dielectric layer. At least one of the control gate and/or the floating gate includes an oxygen scavenging element. The oxygen scavenging element is configured to decrease an oxygen density at least one of at a first interface between the control gate and the high-k dielectric layer, at a second interface between the high-k dielectric layer and the floating gate, at a third interface between the floating gate and the tunnel oxide layer, and at a fourth interface between the tunnel oxide layer and the channel responsive to annealing.

摘要翻译： 提供浮动门装置。 在通道上形成隧道氧化物层。 在隧道氧化物层上形成浮栅。 在浮栅上形成高k电介质层。 在高k电介质层上形成控制栅极。 控制栅极和/或浮动栅极中的至少一个包括氧气清除元件。 氧清除元件被配置为在第k个高k介电层和浮动栅极之间的第二界面处，在第三个控制栅极和高k电介质层之间的第一界面处的至少一个处降低氧气密度 界面在浮动栅极和隧道氧化物层之间，并且在隧道氧化物层和沟道之间的第四界面响应于退火。

公开(公告)号：US20120306019A1

公开(公告)日：2012-12-06

申请号：US13571521

申请日：2012-08-10

申请人： Jin Cai ,  Eduard A. Cartier ,  Martin M. Frank ,  Marwan H. Khater

发明人： Jin Cai ,  Eduard A. Cartier ,  Martin M. Frank ,  Marwan H. Khater

IPC分类号： H01L27/088

CPC分类号： H01L21/823468 ,  H01L21/28176 ,  H01L21/28247 ,  H01L21/823462 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/78

摘要： A semiconductor device includes a first field effect transistor (FET) and a second FET located on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer, wherein the second interfacial oxide layer of the second FET is thicker than the first interfacial oxide layer of the first FET; and a recess located in the substrate adjacent to the second FET.

摘要翻译： 半导体器件包括位于衬底上的第一场效应晶体管（FET）和第二FET，所述第一FET包括第一界面氧化物层，所述第二FET包括第二界面氧化物层，其中所述第二界面氧化物层 第二FET比第一FET的第一界面氧化物层厚; 以及位于与第二FET相邻的衬底中的凹部。

公开(公告)号：US20120193716A1

公开(公告)日：2012-08-02

申请号：US13442087

申请日：2012-04-09

申请人： Martin M. Frank

发明人： Martin M. Frank

IPC分类号： H01L29/772

CPC分类号： H01L21/28247 ,  H01L21/2807 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/3105 ,  H01L21/326 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A semiconductor structure includes a high-k dielectric layer over a semiconductor substrate; and a gate layer over the high-k dielectric layer, wherein the gate layer has a negative electrical bias during anneal.

摘要翻译： 半导体结构包括半导体衬底上的高k电介质层; 以及在高k电介质层上的栅极层，其中栅极层在退火期间具有负电偏压。

公开(公告)号：US20120193348A1

公开(公告)日：2012-08-02

申请号：US13442090

申请日：2012-04-09

申请人： Martin M. Frank

发明人： Martin M. Frank

IPC分类号： H05B3/02

CPC分类号： H01L21/28247 ,  H01L21/2807 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/3105 ,  H01L21/326 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： An apparatus includes a wafer annealing tool and a plurality of electrodes coupled to the wafer annealing tool, wherein the electrodes are configured to be in physical contact with a wafer so that, when the wafer is annealed, a negative electrical bias is formed across one or more gate stacks of the wafer.

摘要翻译： 一种设备包括晶片退火工具和耦合到晶片退火工具的多个电极，其中电极被配置为与晶片物理接触，使得当晶片退火时，负电偏压跨越一个或 更多的晶片堆叠。

公开(公告)号：US20110143482A1

公开(公告)日：2011-06-16

申请号：US13005821

申请日：2011-01-13

申请人： Solomon Assefa ,  Jack O. Chu ,  Martin M. Frank ,  William M. Green ,  Young-hee Kim ,  George G. Totir ,  Joris Van Campenhout ,  Yurri A. Vlasov ,  Ying Zhang

发明人： Solomon Assefa ,  Jack O. Chu ,  Martin M. Frank ,  William M. Green ,  Young-hee Kim ,  George G. Totir ,  Joris Van Campenhout ,  Yurri A. Vlasov ,  Ying Zhang

IPC分类号： H01L31/18

CPC分类号： H01L31/1804 ,  B82Y20/00 ,  G02B6/12004 ,  G02B6/136 ,  G02B2006/12123 ,  H01L31/109 ,  H01L31/1812 ,  Y02E10/547 ,  Y02P70/521

摘要： A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.

摘要翻译： 在第一外延硅层的顶表面上外延地形成第一硅锗合金层，第二外延硅层，第二硅锗层和锗层的垂直叠层。 第二外延硅层，第二硅锗层和锗层通过介电盖部分，电介质间隔物和第一硅锗层被图案化和封装。 在第一和第二硅层之间去除硅锗层以形成硅锗台面结构，其结构上支撑包括硅部分，硅锗合金部分，锗光电检测器和介电帽部分的叠层的悬垂结构。 锗光电探测器由硅锗台面结构悬挂而不邻接硅波导。 锗扩散到硅波导和锗检测器中的缺陷密度被最小化。

公开(公告)号：US20100320547A1

公开(公告)日：2010-12-23

申请号：US12487248

申请日：2009-06-18

申请人： Takashi Ando ,  Changhwan Choi ,  Martin M. Frank ,  Vijay Narayanan

发明人： Takashi Ando ,  Changhwan Choi ,  Martin M. Frank ,  Vijay Narayanan

IPC分类号： H01L29/78 ,  H01L21/314 ,  H01L21/336

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy→2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.

摘要翻译： 高k栅极电介质和金属栅极结构的堆叠包括下部金属层，清除金属层和上部金属层。 清除金属层满足以下两个标准：1）反应Si + 2 / y MxOy→2x / y M + SiO2的吉布斯自由能变化为正的金属（M）2）具有更负的金属 每个氧原子吉布斯自由能用于形成氧化物，而不是下金属层的材料和上金属层的材料。 符合这些标准的清除金属层随着氧原子通过栅电极向高k栅极电介质扩散而捕获氧原子。 此外，清除金属层远远地降低了高k电介质下面的氧化硅界面层的厚度。 结果，即使在CMOS积分期间的高温处理之后，总栅极电介质的等效氧化物厚度（EOT）减小，并且场效应晶体管保持恒定的阈值电压。

公开(公告)号：US07838908B2

公开(公告)日：2010-11-23

申请号：US12359520

申请日：2009-01-26

申请人： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

发明人： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

IPC分类号： H01L27/10

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/517

摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.

摘要翻译： 半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层 第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且 第三金属层，第三金属层设置在第二中间层上。 或者，省略第一金属层。 制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。