公开(公告)号：US20090102487A1

公开(公告)日：2009-04-23

申请号：US11875001

申请日：2007-10-19

Applicant: Moises Cases ,  Bradley Donald Herrman ,  Kent Barclay Howieson ,  Erdem Matoglu ,  Bhyrav Murthy Mutnury ,  Pravin Patel ,  Nam Huu Pham ,  Celeb James Wesley

Inventor： Moises Cases ,  Bradley Donald Herrman ,  Kent Barclay Howieson ,  Erdem Matoglu ,  Bhyrav Murthy Mutnury ,  Pravin Patel ,  Nam Huu Pham ,  Celeb James Wesley

IPC: G01R31/02 ,  G01K3/00 ,  G01N25/72

CPC classification number: G01N25/72 ,  G01J5/0096 ,  G01R31/2818 ,  G01R31/2837 ,  G01R31/309

Abstract: A method for testing a printed circuit board to determining the dielectric loss associated with the circuit board material relative to a standard. Dielectric losses in the material generate heat when a high frequency electronic signal, such as a microwave frequency signal, is communicated through a microstrip that is embedded within the printed circuit board. The temperature or spectrum at the surface of printed circuit board is measured and compared against the temperature or spectrum of the standard to determine whether the material under test is acceptable. While various temperature measurement devices may be used, the temperature is preferably measured without contacting the surface, such as using an infrared radiation probe.

Abstract translation: 一种用于测试印刷电路板以确定与电路板材料相关的介电损耗相对于标准的方法。 当诸如微波频率信号的高频电子信号通过嵌入在印刷电路板内的微带传输时，材料中的介电损耗产生热量。 测量印刷电路板表面的温度或光谱，并与标准品的温度或光谱进行比较，以确定被测材料是否可接受。 尽管可以使用各种温度测量装置，但是优选地在不接触表面的情况下测量温度，例如使用红外辐射探针。

公开(公告)号：US20090021264A1

公开(公告)日：2009-01-22

申请号：US11780505

申请日：2007-07-20

Applicant: Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Nam H. Pham

Inventor： Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Nam H. Pham

IPC: G01R31/02 ,  G06F11/00

CPC classification number: G01R31/2815 ,  G01R31/304 ,  G11C29/02 ,  G11C29/022 ,  G11C29/56 ,  G11C2029/5602

Abstract: The present invention assesses memory (DIMM) strength by calculating frequency content of a radiated field which is collected by an apparatus, such as a dipole antenna. Radiated field is created by accelerated charge, which is a function of the slew rate or DIMM strength. Radiated power is directly proportional to the frequency at which bits are driven. By separating the radiated field from the near field or stored field, the DIMM strength content is isolated from other functional DIMM issues, such as tRCD latency, refresh cycles, addressing mode, etc. By examining the radiated power, the disadvantages of the prior art, such as by probing the DIMM's contacts, are avoided.

Abstract translation: 本发明通过计算由诸如偶极天线的装置收集的辐射场的频率内容来评估存储器（DIMM）强度。 辐射场由加速电荷产生，这是压摆率或DIMM强度的函数。 辐射功率与驱动位的频率成正比。 通过将辐射场与近场或存储场分离，DIMM强度内容与其他功能性DIMM问题（例如tRCD延迟，刷新周期，寻址模式等）隔离。通过检查辐射功率，现有技术的缺点 ，例如通过探测DIMM的触点。

公开(公告)号：US20090007048A1

公开(公告)日：2009-01-01

申请号：US12203335

申请日：2008-09-03

Applicant: MOISES CASES ,  Martin J. Crippen ,  Daniel N. de Araujo ,  Bradley D. Herman ,  Erdem Matoglu ,  William R. Milani ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Nam H. Pham

Inventor： MOISES CASES ,  Martin J. Crippen ,  Daniel N. de Araujo ,  Bradley D. Herman ,  Erdem Matoglu ,  William R. Milani ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Nam H. Pham

IPC: G06F17/50

CPC classification number: H01R25/006

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory module system and DIMM connector is provided. A DIMM connector includes a plurality of DIMM sockets for receiving a corresponding plurality of DIMMs in a radially oriented, angularly spaced orientation. The DIMM sockets are connected in parallel at a memory module junction so that socket terminals of each DIMM socket are joined to the same relative terminal of all the other DIMM sockets along electronic pathways of substantially equal length. A memory controller selectively communicates with the DIMMs via the DIMM junction. By virtue of the improved topology, impedance within the DIMM connector may be better matched to minimize reflections and improve signal quality.

Abstract translation: 提供了体现在用于设计，制造和/或测试存储器模块系统和DIMM连接器的机器可读存储介质中的设计结构。 DIMM连接器包括多个DIMM插座，用于以径向定向的，有角度间隔的方向接收相应的多个DIMM。 DIMM插槽在存储器模块连接处并联连接，使得每个DIMM插座的插座端子沿着基本相等长度的电子路径连接到所有其他DIMM插槽的相同相对端子。 存储器控制器经由DIMM连接器选择性地与DIMM通信。 凭借改进的拓扑结构，可以更好地匹配DIMM连接器内的阻抗以最小化反射并提高信号质量。

公开(公告)号：US20080278207A1

公开(公告)日：2008-11-13

申请号：US11746102

申请日：2007-05-09

Applicant: Henry G. McMillan ,  Pravin Patel ,  Challis L. Purrington ,  Gwendolyn R. Tobin ,  Christopher C. West ,  Ivan R. Zapata

Inventor： Henry G. McMillan ,  Pravin Patel ,  Challis L. Purrington ,  Gwendolyn R. Tobin ,  Christopher C. West ,  Ivan R. Zapata

IPC: H03K5/12

CPC classification number: H03K5/1534 ,  H03K19/01721

Abstract: Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus.

Abstract translation: 本发明的实施例解决了与数字信号传输相关的技术缺陷，并且提供了一种用于USB接口的新颖且不可见的下降时间加速器电路。 在本发明的一个实施例中，USB接口可以包括通过USB总线耦合到主控制器驱动器的USB端口驱动器。 USB接口还可以包括在USB端口驱动器和主机控制器驱动器之间耦合到USB总线的下降时间加速器电路。 下降时间加速器电路可以包括耦合到来自USB总线的入站信号路径的脉冲信号发生器，并且被布置成在检测入站信号路径上的数字信号的下降沿时产生可调脉冲。 电路还可以包括另外耦合到入站信号路径的有源定时器，以将可调谐脉冲保持一段时间。 最后，电路可以包括耦合到来自脉冲信号发生器的出站信号路径的下降驱动信号加强器，该脉冲信号发生器布置成将出站信号路径上的可调谐脉冲释放到USB总线上。

公开(公告)号：US20080188095A1

公开(公告)日：2008-08-07

申请号：US11670015

申请日：2007-02-01

Applicant: Robert Joseph Christopher ,  Pravin Patel ,  Tony Carl Sass

Inventor： Robert Joseph Christopher ,  Pravin Patel ,  Tony Carl Sass

IPC: H01R12/00

CPC classification number: H01R13/6477 ,  H01R13/6471 ,  H01R13/6474 ,  H05K1/024

Abstract: Connector and methods of connector design and manufacture are disclosed for achieving a desired phase relationship between signals carried along conductors of different lengths, while maintaining a desired impedance of the conductors. In one embodiment, a PCB connector includes a first plurality of electronic terminals and a second plurality of electronic terminals disposed on a connector body. A substrate has a dielectric constant that varies with location within the substrate. A first electronic conductor follows a first pathway within the substrate to experience a first effective dielectric constant. A second electronic conductor follows a second pathway within the substrate to experience a second effective dielectric constant. The first electronic conductor is longer than the second electronic conductor and the first effective dielectric constant is less than the second effective dielectric constant, to at least reduce phase error between signals. By satisfying the relationship l1/l2=sqrt(ε2/ε1), a phase error may be avoided.

Abstract translation: 公开连接器和连接器设计和制造的方法，用于在保持导体的期望阻抗的同时实现沿着不同长度的导体携带的信号之间的期望的相位关系。 在一个实施例中，PCB连接器包括第一多个电子端子和设置在连接器主体上的第二多个电子端子。 衬底具有随着衬底内的位置而变化的介电常数。 第一电子导体遵循衬底内的第一路径以经历第一有效介电常数。 第二电子导体遵循衬底内的第二路径以经历第二有效介电常数。 第一电子导体比第二电子导体长，并且第一有效介电常数小于第二有效介电常数，以至少减小信号之间的相位误差。 通过满足关系l 1/2/2 / sqrt（ε2 /ε1 1），相位误差 可以避免。