利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

130 条记录 (耗时 0.029 秒)

    Method and apparatus to electrically qualify high speed PCB connectors
    3.
    发明授权
    Method and apparatus to electrically qualify high speed PCB connectors 有权
    电连接高速PCB连接器的方法和装置

    公开(公告)号：US07525319B1

    公开(公告)日：2009-04-28

    申请号：US12200208

    申请日：2008-08-28

    申请人： Rubina Firdaus Ahmed ,  Moises Cases ,  Bradley Donald Herrman ,  Kent Barclay Howieson ,  Bhyrav Murthy Mutnury ,  Pravin Patel ,  Peter Robert Seidel

    发明人： Rubina Firdaus Ahmed ,  Moises Cases ,  Bradley Donald Herrman ,  Kent Barclay Howieson ,  Bhyrav Murthy Mutnury ,  Pravin Patel ,  Peter Robert Seidel

    IPC分类号： G01R31/04 ,  G01R31/02 ,  G01R31/28

    CPC分类号： G01R31/046

    摘要： A method of electrically qualifying high speed printed circuit board (PCB) connectors includes mounting a PCB connector on a test card, sending bit patterns through a first portion of the test card, evaluating a waveform on a sense signal on a second portion of the test card for the bit patterns launched on said first portion of the test card to measure common mode noise, and comparing the measured common mode noise of the second portion of the test card to a golden standard performed on a pre-qualified connector. The first portion of the test card comprises connectors to inject bit patterns. The second portion of the test card includes a split plane which induces common mode noise on a sense signal, the sense signal, and a termination pack. If the measured common mode noise on the PCB connector is worse than the golden standard, then the PCB connector is disqualified. If the measured common mode noise on the PCB connector is as good as or better than the golden standard, then the PCB connector is qualified. A first section of the PCB connector connects to the first portion of the test card and a second section of the PCB connector connects to the second portion of the test card. Transmission lines in the test card and the sense line are tightly coupled by shortening a distance between the sense line and the transmission lines.

    摘要翻译： 电气限定高速印刷电路板（PCB）连接器的方法包括将PCB连接器安装在测试卡上，通过测试卡的第一部分发送位模式，在测试的第二部分上评估感测信号上的波形 在测试卡的所述第一部分上发射的位模式的卡用于测量共模噪声，以及将测试卡的第二部分的测量的共模噪声与在预先标定的连接器上执行的黄金标准进行比较。 测试卡的第一部分包括用于注入位模式的连接器。 测试卡的第二部分包括在感测信号，感测信号和终端包上引起共模噪声的分离平面。 如果PCB连接器上测得的共模噪声比黄金标准差，则PCB连接器不合格。 如果PCB连接器上测得的共模噪声与黄金标准一样好或更好，则PCB连接器是合格的。 PCB连接器的第一部分连接到测试卡的第一部分，并且PCB连接器的第二部分连接到测试卡的第二部分。 通过缩短感测线和传输线之间的距离，测试卡和感测线中的传输线紧密耦合。

    APPARATUS, SYSTEM, AND METHOD FOR INTEGRATED COMPONENT TESTING
    4.
    发明申请
    APPARATUS, SYSTEM, AND METHOD FOR INTEGRATED COMPONENT TESTING 有权
    用于集成组件测试的装置，系统和方法

    公开(公告)号：US20090079456A1

    公开(公告)日：2009-03-26

    申请号：US11859540

    申请日：2007-09-21

    申请人： Moises Cases ,  Shiva R. Dasari ,  Erdem Matoglu ,  Bhyrav Murthy Mutnury ,  Nam Huu Pham

    发明人： Moises Cases ,  Shiva R. Dasari ,  Erdem Matoglu ,  Bhyrav Murthy Mutnury ,  Nam Huu Pham

    IPC分类号： G01R31/02

    CPC分类号： G06F11/24 ,  G11C5/04 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/50 ,  G11C2029/5004

    摘要： An apparatus, system, and method are disclosed for integrating component testing. A voltage module modifies a reference voltage integral to an electronic device to a plurality of reference voltage values. A test module tests a component of the electronic device at each of the plurality of reference voltage values. In addition, the test module determines a voltage range for the component, wherein the voltage range comprises voltage values between a high voltage failure and a low voltage failure. An optimization module sets the reference voltage value to within the voltage range.

    摘要翻译： 公开了用于集成部件测试的装置，系统和方法。 电压模块将对电子设备积分的参考电压修改为多个参考电压值。 测试模块在多个参考电压值中的每一个测试电子设备的组件。 此外，测试模块确定组件的电压范围，其中电压范围包括高电压故障和低电压故障之间的电压值。 优化模块将参考电压值设置在电压范围内。

    Conductor cable having a high surface area
    5.
    发明授权
    Conductor cable having a high surface area 有权
    导体电缆具有较高的表面积

    公开(公告)号：US07479597B1

    公开(公告)日：2009-01-20

    申请号：US11946165

    申请日：2007-11-28

    申请人： Moises Cases ,  Daniel N. de Araujo ,  Bhyrav Murthy Mutnury ,  Nam Huu Pham ,  Bruce James Wilkie

    发明人： Moises Cases ,  Daniel N. de Araujo ,  Bhyrav Murthy Mutnury ,  Nam Huu Pham ,  Bruce James Wilkie

    IPC分类号： H01B7/00

    CPC分类号： H01B7/30 ,  H01B7/0009

    摘要： A cable having an electrically conducting wire with a cross sectional shape defined by a simple closed curve having from three to eight concave portions separated by an equal number of convex portions. The simple closed curve has no point where the radius of curvature is less than one-sixth (⅙) of an overall radius of the wire and no point where adjacent curves or lines intersect at an angle. The alternating concave and convex portions of the cable's cross-sectional shape may have substantially the same curvature. The cross-sectional shape of the cable avoids sharp angles and fight curves.

    摘要翻译： 一种具有导线的电缆，其横截面形状由简单的闭合曲线限定，具有由相等数量的凸部分开的三至八个凹部。 简单的闭合曲线没有点曲率半径小于线的总半径的六分之一（1/6），而相邻的曲线或线不是以一定角度相交的点。 电缆的横截面形状的交替的凹凸部分可以具有基本相同的曲率。 电缆的横截面形状避免了锐角和抗弯曲。

    Multi-memory module circuit topology
    7.
    发明申请
    Multi-memory module circuit topology 审中-公开
    多内存模块电路拓扑

    公开(公告)号：US20070257699A1

    公开(公告)日：2007-11-08

    申请号：US11407814

    申请日：2006-04-20

    申请人： Moises Cases ,  Daniel De Araujo ,  Erdem Matoglu ,  Pravin Patel ,  Nam Pham

    发明人： Moises Cases ,  Daniel De Araujo ,  Erdem Matoglu ,  Pravin Patel ,  Nam Pham

    IPC分类号： H03K17/16

    CPC分类号： G11C5/04 ,  G11C5/063

    摘要： A multi-memory module circuit topology is disclosed that includes a memory controller, a plurality of memory modules connected to the memory controller through a memory bus, and a resonator connected to the plurality of memory modules in a starburst topology. A method for reducing impedance discontinuities in a multi-memory module circuit is disclosed that includes providing a plurality of memory modules connected to a memory controller through a memory bus, selecting a starburst topology, and connecting a resonator to the plurality of memory module in dependence upon the selected starburst topology. An additional method for reducing impedance discontinuities in a multi-memory module circuit is disclosed that includes providing by a resonator a predetermined discontinuity reducing impedance at a predetermined location in the multi-memory module circuit between at least two memory modules, the multi-memory module circuit having a plurality of components of logically arranged around the predetermined location.

    摘要翻译： 公开了一种多存储器模块电路拓扑，其包括存储器控制器，通过存储器总线连接到存储器控制器的多个存储器模块，以及以星爆拓扑连接到多个存储器模块的谐振器。 公开了一种用于减少多存储器模块电路中的阻抗不连续性的方法，其包括通过存储器总线提供连接到存储器控制器的多个存储器模块，选择星爆拓扑，并且依次将谐振器连接到多个存储器模块 在选定的星爆拓扑上。 公开了一种用于减少多存储器模块电路中的阻抗不连续性的附加方法，其包括由谐振器在至少两个存储器模块之间的多存储器模块电路中的预定位置处提供预定的不连续性减小阻抗，所述多存储器模块 电路具有围绕预定位置逻辑布置的多个部件。

    High-speed routing composite material
    8.
    发明申请
    High-speed routing composite material 审中-公开
    高速路由复合材料

    公开(公告)号：US20070178289A1

    公开(公告)日：2007-08-02

    申请号：US11340907

    申请日：2006-01-27

    申请人： Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Pravin Patel ,  Nam H. Pham ,  Joffre A. Ratcliffe

    发明人： Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Pravin Patel ,  Nam H. Pham ,  Joffre A. Ratcliffe

    IPC分类号： B32B3/00

    CPC分类号： B32B17/04 ,  H05K1/0248 ,  H05K1/025 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/09227 ,  Y10T428/24917

    摘要： An electronic system includes a circuit board formed from a composite material. The composite material includes fibers embedded within a substrate and the fibers are oriented substantially orthogonal to one another. A plurality of traces are formed on the board, and the plurality of traces are oriented relative to at least one of the fibers at an angle between about 17.5° and about 27.5° or between about 20.0° and about 25.0°. A pair of the traces are oriented substantially orthogonal to one another, and a pair of the traces are oriented relative to one another at an angle of about 45.0°. The fibers are fiberglass, and the substrate is an epoxy resin. The fibers have a different dielectric constant than the substrate.

    摘要翻译： 电子系统包括由复合材料形成的电路板。 复合材料包括嵌入基片内的纤维，纤维彼此基本正交。 在板上形成多个迹线，并且多个迹线相对于至少一个光纤以约17.5°至约27.5°之间的角度或约20.0°至约25.0°的角度定向。 一对迹线基本上彼此正交地定向，并且一对迹线以大约45.0°的角度相对于彼此定向。 纤维是玻璃纤维，基材是环氧树脂。 纤维的介电常数不同于基材。

    MINIMIZING PLATING STUB REFLECTIONS IN A CHIP PACKAGE USING CAPACITANCE
    10.
    发明申请
    MINIMIZING PLATING STUB REFLECTIONS IN A CHIP PACKAGE USING CAPACITANCE 有权
    使用电容最小化芯片包装中的镀层反射

    公开(公告)号：US20100073893A1

    公开(公告)日：2010-03-25

    申请号：US12237444

    申请日：2008-09-25

    申请人： Bhyrav Murthy Mutnury ,  Moises Cases ,  Nanju Na ,  Tae Hong Kim

    发明人： Bhyrav Murthy Mutnury ,  Moises Cases ,  Nanju Na ,  Tae Hong Kim

    IPC分类号： H05K7/00 ,  H01L21/00

    CPC分类号： H01L21/4853 ,  C25D5/02 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/162 ,  H05K3/242 ,  H05K2203/049 ,  H01L2924/00012 ,  H01L2924/00

    摘要： Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.

    摘要翻译： 本发明的实施例涉及通过连接开放式电镀短截线和接地之间的电容来将高频芯片封装中的谐振频率从工作频率移开。 一个实施例提供了用于将芯片与印刷电路板接口的多层基板。 第一外层提供了芯片安装位置。 信号互连与芯片安装位置间隔开，并且信号迹线从芯片安装位置附近延伸到信号互连。 安装在芯片安装位置的芯片可以通过引线键合连接到信号迹线。 电镀短截线从信号互连延伸到衬底的周围。 电容器用于将电镀端子电容耦合到接地层。