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    METHOD OF INTEGRATED CIRCUIT CHIP FABRICATION AND PROGRAM PRODUCT THEREFOR
    51.
    发明申请
    METHOD OF INTEGRATED CIRCUIT CHIP FABRICATION AND PROGRAM PRODUCT THEREFOR 有权
    集成电路芯片制造方法及其程序产品

    公开(公告)号：US20100318956A1

    公开(公告)日：2010-12-16

    申请号：US12482504

    申请日：2009-06-11

    申请人： Geng Han ,  Fook-Luen Heng ,  Jin Fuw Lee ,  Chao Yi Tien ,  Rama N. Singh

    发明人： Geng Han ,  Fook-Luen Heng ,  Jin Fuw Lee ,  Chao Yi Tien ,  Rama N. Singh

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A method of physical design for integrated circuit (IC) chip fabrication, physical design system and program product therefor. A design shape is fragmented into segments for Optical Proximity Correction (OPC) and a harmonic mean of the segments is determined. Electrical intent is determined for the shape and a harmonic mean is determined for the segments. Segments may be moved based on a effect on the harmonic mean from moving the segments, measured using a harmonic mean cost function. Finally segmented shapes are passed to OPC.

    摘要翻译： 一种用于集成电路（IC）芯片制造，物理设计系统及其程序产品的物理设计方法。 设计形状被分段为光学邻近校正（OPC）的段，并确定段的谐波平均值。 根据形状确定电气意图，并为段确定谐波平均值。 可以基于使用谐波平均成本函数测量的移动段的对谐波平均值的影响来移动段。 最后分段形状传递给OPC。

    SYSTEM AND METHOD FOR EMPLOYING PATTERNING PROCESS STATISTICS FOR GROUND RULES WAIVERS AND OPTIMIZATION
    55.
    发明申请
    SYSTEM AND METHOD FOR EMPLOYING PATTERNING PROCESS STATISTICS FOR GROUND RULES WAIVERS AND OPTIMIZATION 有权
    用于接地规则的绘图过程统计的系统和方法和优化

    公开(公告)号：US20080301624A1

    公开(公告)日：2008-12-04

    申请号：US12175097

    申请日：2008-07-17

    申请人： Fook-Luen Heng ,  Mark Alan Lavin ,  Jin-Fuw Lee ,  Chieh-yu Lin ,  Jawahar Pundalik Nayak ,  Rama Nand Singh

    发明人： Fook-Luen Heng ,  Mark Alan Lavin ,  Jin-Fuw Lee ,  Chieh-yu Lin ,  Jawahar Pundalik Nayak ,  Rama Nand Singh

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules for compliance by the layout. The process variation distributions are mapped to an intersect area distribution by creating a histogram based upon a plurality of processes for an intersect area. The intersect area is analyzed using the histogram to provide ground rule waivers and optimization.

    摘要翻译： 使用图案化处理统计来评估交叉区域分析的布局的系统和方法包括对布局应用光学近似校正（OPC），模拟由掩模形成的图像并应用图案化过程变化分布来影响和确定纠正措施以改进和 优化布局符合规则。 通过基于交叉区域的多个处理创建直方图，将过程变化分布映射到交叉区域分布。 使用直方图分析交叉区域，以提供基本规则豁免和优化。

    Method to Determine the Root Causes of Failure Patterns by Using Spatial Correlation of Tester Data
    56.
    发明申请
    Method to Determine the Root Causes of Failure Patterns by Using Spatial Correlation of Tester Data 失效
    通过使用测试者数据的空间相关性来确定故障模式的根本原因的方法

    公开(公告)号：US20080301597A1

    公开(公告)日：2008-12-04

    申请号：US11754947

    申请日：2007-05-29

    申请人： Howard Chen ,  Katherine V. Hawkins ,  Fook-Luen Heng ,  Louis Hsu ,  Xu Ouyang

    发明人： Howard Chen ,  Katherine V. Hawkins ,  Fook-Luen Heng ,  Louis Hsu ,  Xu Ouyang

    IPC分类号： G06F17/50

    CPC分类号： G01R31/2894 ,  G01R31/31718 ,  G01R31/318314 ,  G11C29/10 ,  G11C29/56 ,  G11C29/56008

    摘要： A method for determining the root causes of fail patterns in integrated circuit chips is provide wherein a known integrated circuit chip layout is used to identify a plurality of potential defects and a plurality of potential fail patterns in the integrated circuit chip. Correlations between the potential defects and the potential fail patterns that result from those defects are identified. Based on this identification, the potential fail patterns are grouped by common potential defect. An actual integrated circuit chip that is manufactured in accordance with the test layout is tested for failure patterns. These failure patterns are then compared to the groupings of potential fail patterns. When a match is found, that is when a given group of fail patterns is found in the actual integrated circuit chip, then the potential defect associated with the potential fail patterns to which the actual fail patterns are matched is identified. This defect is the root cause of the failure pattern in the actual chip.

    摘要翻译： 提供了一种用于确定集成电路芯片中的故障模式的根本原因的方法，其中使用已知的集成电路芯片布局来识别集成电路芯片中的多个潜在缺陷和多个潜在故障模式。 鉴定出潜在缺陷与由这些缺陷产生的潜在失效模式之间的相关性。 基于此识别，潜在的故障模式由共同的潜在缺陷分组。 测试根据测试布局制造的实际集成电路芯片的故障模式。 然后将这些故障模式与潜在故障模式的分组进行比较。 当发现匹配时，即在实际的集成电路芯片中发现给定的一组故障模式时，识别与实际故障模式匹配的潜在故障模式相关联的潜在缺陷。 这个缺陷是实际芯片中故障模式的根本原因。

    INTEGRATED CIRCUIT SELECTIVE SCALING
    59.
    发明申请
    INTEGRATED CIRCUIT SELECTIVE SCALING 有权
    集成电路选择性缩放

    公开(公告)号：US20060085768A1

    公开(公告)日：2006-04-20

    申请号：US10711959

    申请日：2004-10-15

    申请人： Fook-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Stephen Runyon ,  Robert Walker

    发明人： Fook-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Stephen Runyon ,  Robert Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.

    摘要翻译： 公开了用于选择性地缩放集成电路（IC）设计的方法，系统和程序产品：按层，单元或基本规则，或这些的组合。 在设计寿命期间，选择性缩放技术可以应用于具有过程和产量反馈的制造系统的反馈回路中，以便以保持层次结构的方式增加早期过程中的产量。 本发明消除了在实现诸如无掩模制造之类的新技术的情况下使设计人员改进产量的需要。

    Optimized phase shift design migration
    60.
    发明授权
    Optimized phase shift design migration 失效
    优化的相移设计迁移

    公开(公告)号：US6083275A

    公开(公告)日：2000-07-04

    申请号：US5613

    申请日：1998-01-09

    申请人： Fook-Luen Heng ,  Lars W. Liebmann

    发明人： Fook-Luen Heng ,  Lars W. Liebmann

    IPC分类号： G03F1/00 ,  G06F17/50 ,  G06F7/60 ,  G03F5/00 ,  G03F9/00 ,  G06F17/10

    CPC分类号： G06F17/5081

    摘要： A method for converting an integrated circuit design to a phase-shift complaint mask design. The method comprises the steps of locating features of the integrated circuit that violate predetermined design criteria converting error flags to physical marker shapes, modifying the located features using layout modification system technology based on a predetermined cost constraint, determining if all violations are corrected, and either changing the cost constraint to a higher cost constraint if violations still exist and repeating the process or terminating the conversion if all violations are corrected.

    摘要翻译： 一种用于将集成电路设计转换为相移投诉掩模设计的方法。 该方法包括以下步骤：确定违反预定设计准则的特征，将错误标志转换为物理标记形状，使用基于预定成本约束的布局修改系统技术来修改所定位的特征，确定是否所有违规被校正，以及 如果违反行为仍然存在并将重复该过程或终止转换（如果所有违规行为已更正），则将成本约束更改为更高的成本约束。