公开(公告)号：US11901288B2

公开(公告)日：2024-02-13

申请号：US16924968

申请日：2020-07-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba ,  Shinichi Uchida

IPC: H03F3/187 ,  H01L23/522 ,  H01L49/02 ,  H03M1/12 ,  H03F3/04

CPC classification number: H01L23/5227 ,  H01L23/5226 ,  H01L28/10 ,  H03F3/04 ,  H03M1/12

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element, and a multilayer wiring. The semiconductor element is formed on the semiconductor substrate. The multilayer wiring includes a wiring electrically connected with the semiconductor element, and a first inductor. The multilayer wiring is formed on the semiconductor substrate such that the multilayer wiring covers the semiconductor element. The first inductor is formed such that the first inductor electrically isolated from the wiring and is magnetically connected with the wiring.

公开(公告)号：US11705433B2

公开(公告)日：2023-07-18

申请号：US17380653

申请日：2021-07-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka Nakashiba

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/5227 ,  H01L24/32 ,  H01L2224/32145 ,  H01L2225/06531 ,  H01L2225/06544

Abstract: A semiconductor device includes a first semiconductor chip, an adhesive layer that is formed on the first semiconductor chip, and a second semiconductor chip that is arranged on the first semiconductor chip via the adhesive layer. The first semiconductor chip has a first semiconductor substrate and a first wiring layer. The first wiring layer has a first inductor and a first electrode pad. The first wiring layer is formed on the first semiconductor substrate. The second semiconductor chip has a second wiring layer and a second semiconductor substrate. The second wiring layer is formed on the first wiring layer via the adhesive layer. The second semiconductor substrate is formed on the second wiring layer, and has a first opening. In a plan view, the first electrode pad is formed so as not to overlap with the second semiconductor chip, and a second electrode pad overlaps with the first opening.

公开(公告)号：US11183471B2

公开(公告)日：2021-11-23

申请号：US16681329

申请日：2019-11-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka Nakashiba

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/66

Abstract: A semiconductor device includes a semiconductor substrate, a multilayer wiring layer, a first inductor element, and a first capacitor element. The multilayer wiring layer is formed on the semiconductor substrate. The first inductor element and the first capacitor element are formed in the multilayer wiring layer. The first capacitor element is formed in the same layer as a layer in which the first inductor element is formed. The first capacitor element is formed inside the first inductor element in plan view.

公开(公告)号：US11145597B2

公开(公告)日：2021-10-12

申请号：US16505228

申请日：2019-07-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Kuwabara ,  Yasutaka Nakashiba ,  Teruhiro Kuwajima

IPC: H01L23/522 ,  H01L23/495 ,  H01L23/00 ,  H01L21/762 ,  H01L21/8238 ,  H01L23/528 ,  H01L21/768 ,  H01L27/092 ,  H01L27/06

Abstract: A semiconductor device includes a first semiconductor chip on which a first circuit is formed and a second semiconductor chip on which two circuits are formed. In the first semiconductor chip, a first inductor on the transmitting side electrically connected with the first circuit and a second inductor on the receiving side electrically connected with the second circuit via the bonding wire are formed. In plan view, the first inductor and the second inductor are disposed so as not to overlap each other, and are arranged along each other.

公开(公告)号：US11002997B2

公开(公告)日：2021-05-11

申请号：US16722394

申请日：2019-12-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Seigo Namioka ,  Yasutaka Nakashiba

IPC: G02F1/025

Abstract: A semiconductor device includes a first insulating layer, an optical waveguide formed on the first insulating layer, a fixed charge layer formed on the first insulating layer such that the fixed charge layer covers the optical waveguide, and a second insulating layer formed on the fixed charge layer.

公开(公告)号：US10921514B2

公开(公告)日：2021-02-16

申请号：US16438067

申请日：2019-06-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

IPC: G02B6/036 ,  G02B6/42 ,  G02B6/30 ,  G02B6/32 ,  G02B6/125

Abstract: The semiconductor device includes an optical waveguide WG1 formed in a planar manner, and a three-dimensional optical waveguide WG2 optically connected with the optical waveguide WG1 and including a curved shape.

公开(公告)号：US10818591B2

公开(公告)日：2020-10-27

申请号：US15953872

申请日：2018-04-16

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida ,  Yasutaka Nakashiba ,  Tetsuya Iida ,  Shinichi Kuwabara

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768 ,  H01L21/3213 ,  H01L25/065 ,  H01L23/532 ,  H04B5/00

Abstract: A method of manufacturing a semiconductor device includes a step of: patterning a conductive film formed over an interlayer insulating film so as to form a coil and a conductive pattern in the same layer, and then forming unevennesses on a surface of the interlayer insulating film by etching a portion of the interlayer insulating film with using the coil and the conductive pattern as a mask.

公开(公告)号：US10466415B2

公开(公告)日：2019-11-05

申请号：US15961435

申请日：2018-04-24

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka Nakashiba ,  Shinichi Watanuki

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/124 ,  G02B6/136 ,  G02F1/025 ,  G02B6/34

Abstract: A semiconductor device including an optical waveguide and a p-type semiconductor portion is configured as follows. The optical waveguide includes: a first semiconductor layer formed on an insulating layer; an insulating layer formed on the first semiconductor layer; and a second semiconductor layer formed on the insulating layer. The p-type semiconductor portion includes the first semiconductor layer. The film thickness of the p-type semiconductor portion is smaller than that of the optical waveguide. By forming the insulating layer between the first semiconductor layer and the second semiconductor layer, control of the film thicknesses of the optical waveguide and the p-type semiconductor portion is facilitated. Specifically, when the unnecessary second semiconductor layer is removed by etching in a step of forming the p-type semiconductor portion, the insulating layer which is the lower layer functions as an etching stopper, and the film thickness of the p-type semiconductor portion can be easily adjusted.

公开(公告)号：US10290577B2

公开(公告)日：2019-05-14

申请号：US16009429

申请日：2018-06-15

Applicant: Renesas Electronics Corporation

Inventor： Teruhiro Kuwajima ,  Akira Matsumoto ,  Yasutaka Nakashiba ,  Takashi Iwadare

IPC: H01L23/495 ,  H01L23/522

Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.

公开(公告)号：US10236371B2

公开(公告)日：2019-03-19

申请号：US15403539

申请日：2017-01-11

Applicant: Renesas Electronics Corporation

Inventor： Tohru Kawai ,  Yasutaka Nakashiba ,  Yutaka Akiyama

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L27/07 ,  H01L29/06 ,  H01L29/10 ,  H01L23/495 ,  H01L23/522 ,  H01L23/00

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.