公开(公告)号：US07605032B2

公开(公告)日：2009-10-20

申请号：US11529446

申请日：2006-09-28

申请人： Richard Johannes Luyken ,  Hans-Peter Moll ,  Martin Popp ,  Till Schloesser ,  Marc Strasser ,  Rolf Weis

发明人： Richard Johannes Luyken ,  Hans-Peter Moll ,  Martin Popp ,  Till Schloesser ,  Marc Strasser ,  Rolf Weis

IPC分类号： H01L21/334 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/94 ,  H01L21/336 ,  H01L27/088

CPC分类号： H01L21/26586 ,  H01L29/66537 ,  H01L29/66621 ,  H01L29/7834

摘要： In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.

摘要翻译： 在制造沟槽晶体管的方法中，提供第一导电类型的衬底，并且形成衬底中的沟槽和沟槽中的栅极电介质。 形成沟槽中作为栅极电介质和第一源极和漏极区域上的栅电极的第一导电填充物。 蚀刻后的第一导电填充物是通过将第一导电填料向下蚀刻回到低于第一源的深度并形成漏极区和第二源极和漏极区而产生的。 第二源极和漏极区域与第一源极和漏极区域相邻并且延伸至至少与蚀刻后的第一导电填充物一样深的深度。 在所述沟槽中形成有在所述蚀刻后的第一导电填充物上方的绝缘间隔物，并且在所述沟槽中设置第二导电填充物作为所述栅电极的上部。

公开(公告)号：US20090206316A1

公开(公告)日：2009-08-20

申请号：US12033533

申请日：2008-02-19

申请人： Rolf Weis ,  Thomas Happ

发明人： Rolf Weis ,  Thomas Happ

IPC分类号： H01L45/00

CPC分类号： H01L27/24

摘要： An integrated circuit includes a U-shaped access device and a first line coupled to a first side of the access device. The integrated circuit includes a contact coupled to a second side of the access device and self-aligned dielectric material isolating the first line from the contact.

摘要翻译： 集成电路包括U形接入设备和耦合到接入设备的第一侧的第一线路。 集成电路包括耦合到存取装置的第二侧的触点和将第一线与触点隔离的自对准电介质材料。

公开(公告)号：US07442609B2

公开(公告)日：2008-10-28

申请号：US11222613

申请日：2005-09-09

申请人： Peng-Fei Wang ,  Joachim Nuetzel ,  Rolf Weis ,  Till Schloesser ,  Marc Strasser ,  Richard Johannes Luyken

发明人： Peng-Fei Wang ,  Joachim Nuetzel ,  Rolf Weis ,  Till Schloesser ,  Marc Strasser ,  Richard Johannes Luyken

IPC分类号： H01L21/336

CPC分类号： H01L27/10823 ,  G11C11/404 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

摘要： A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the trenches at a position adjacent to the groove so that the two plate-like portions will be connected with the groove and the groove is disposed between two plate-like portions. In one embodiment, the two plate-like portions are defined by an etching process which selectively etches the isolating material of the isolation trenches with respect to the semiconductor substrate material. A gate insulating material is provided at an interface between the active area and the groove and the interface between the active area and the plate-like portions, and a gate electrode material is deposited so as to fill the groove and the two plate-like portions.

摘要翻译： 一种制造晶体管的方法。 在一个实施例中，该方法包括通过在衬底中限定栅极沟槽来形成栅电极。 在与沟槽相邻的位置上的每个沟槽中限定了板状部分，使得两个板状部分将与沟槽连接，并且沟槽设置在两个板状部分之间。 在一个实施例中，通过蚀刻工艺限定两个板状部分，该蚀刻工艺相对于半导体衬底材料选择性地蚀刻隔离沟槽的隔离材料。 栅极绝缘材料设置在有源区域和沟槽之间的界面以及有源区域和板状部分之间的界面处，并且沉积栅电极材料以填充沟槽和两个板状部分 。

公开(公告)号：US20080182378A1

公开(公告)日：2008-07-31

申请号：US11669613

申请日：2007-01-31

申请人： Ulrike Gruening-von Schwerin ,  Rolf Weis ,  Wolfgang Henke ,  Odo Wunnicke ,  Till Schloesser ,  Florian Schnabel ,  Wolfgang Mueller

发明人： Ulrike Gruening-von Schwerin ,  Rolf Weis ,  Wolfgang Henke ,  Odo Wunnicke ,  Till Schloesser ,  Florian Schnabel ,  Wolfgang Mueller

IPC分类号： H01L21/20

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91

摘要： A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.

摘要翻译： 公开了一种形成具有电容器的集成电路的方法。 在一个实施例中，该方法包括形成具有第一电极，电介质层和第二电极的电容器元件。 电容器元件使用支撑层形成。

公开(公告)号：US20070290248A1

公开(公告)日：2007-12-20

申请号：US11452745

申请日：2006-06-14

申请人： Rolf Weis

发明人： Rolf Weis

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/0207 ,  H01L27/10829 ,  H01L27/10867

摘要： The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding semiconductor structure. The method comprises the steps of: providing a semiconductor substrate having a plurality of trench capacitors which are arranged in rows and columns in a checkerboard layout; forming connection straps for electrically connecting said trench capacitors such that the connection straps of pairs of adjacent columns are facing each other, forming insulation trenches between said rows for defining active areas, each of which active areas is electrically connected to a connection strap of an associated trench capacitor on a first side and each of which is electrically insulated from a neighboring trench capacitor of said associated trench capacitor on a second side; forming electrically conducting landing pads between adjacent active areas for connecting pairs of said active areas, said landing pads being arranged in first lines in parallel to said columns; forming an insulation layer on said first insulating layer covering said landing pads; and forming a cell transistor for each trench capacitor which divides the active area of the associated trench capacitor in a first and second section, said cell transistors being arranged in second lines in parallel to said columns.

摘要翻译： 本发明提供了一种用于集成半导体结构和相应的半导体结构的制造方法。 该方法包括以下步骤：提供具有多个沟槽电容器的半导体衬底，其以棋盘布局的行和列布置; 形成用于电连接所述沟槽电容器的连接带，使得成对的相邻列的连接带彼此面对，在所述行之间形成用于限定有源区域的绝缘沟槽，每个有源区域电连接到相关联的连接带 沟槽电容器在第一侧上，并且每个沟槽电容器与第二侧上的所述相关联的电容器的相邻沟槽电容器电绝缘; 在相邻的有效区域之间形成用于连接所述有源区域对的导电接地焊盘，所述着陆焊盘以与所述列平行的第一线布置; 在覆盖所述着陆焊盘的所述第一绝缘层上形成绝缘层; 以及为在第一和第二部分中划分相关的沟槽电容器的有源区的每个沟槽电容器形成单元晶体管，所述单元晶体管被布置在与所述列平行的第二行中。

公开(公告)号：US20070096182A1

公开(公告)日：2007-05-03

申请号：US11556897

申请日：2006-11-06

申请人： Till Schloesser ,  Rolf Weis ,  Ulrike Gruening-von Schwerin

发明人： Till Schloesser ,  Rolf Weis ,  Ulrike Gruening-von Schwerin

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： G11C11/404 ,  H01L27/0207 ,  H01L27/10873 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7854

摘要： A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically isolated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.

摘要翻译： 公开了晶体管，存储单元阵列和制造晶体管的方法。 在一个实施例中，本发明涉及至少部分地形成在半导体衬底中的晶体管，包括第一和第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域，所述沟道区域是 设置在所述半导体衬底中，以及栅电极，沿着所述沟道区设置并与所述沟道区电隔离，用于控制在所述第一和第二源/漏区之间流动的电流，其中所述沟道区包括 所述通道具有脊的形状，所述脊包括垂直于连接所述第一和第二源极/漏极区的线的横截面中的顶侧和两个侧边，其中所述顶侧设置在所述半导体的表面下方 基板和所述栅电极沿着所述顶侧和所述两个横向侧面设置。

公开(公告)号：US07208373B2

公开(公告)日：2007-04-24

申请号：US11140143

申请日：2005-05-27

申请人： Rolf Weis

发明人： Rolf Weis

IPC分类号： H01L21/8142

CPC分类号： H01L27/10876 ,  H01L27/10855 ,  H01L27/10867 ,  H01L27/10879 ,  H01L29/785

摘要： A method of forming a memory cell array comprising a plurality of memory cells, each of the memory cells including a trench capacitor and a transistor is disclosed. In one embodiment, during the formation of the transistors, after the definition of isolation trenches and corresponding active areas, providing a gate electrode comprises etching the insulating material in the isolation trenches at a portion adjacent to the channel so that a portion of the channel is uncovered, the portion having the shape of ridge comprising a top side and two lateral sides, providing a gate insulating layer on the top side and the two lateral sides, providing a conducting material on the gate insulating layer so that as a result the gate electrode is disposed along the top side and the two lateral sides of the channel, wherein etching the insulating material in the isolation trenches is performed in which the insulating material is locally etched, wherein the insulating material in the upper portion of insulation grooves which separate active areas from each other is maintained.

摘要翻译： 公开了一种形成包括多个存储单元的存储单元阵列的方法，每个存储单元包括沟槽电容器和晶体管。 在一个实施例中，在晶体管的形成期间，在隔离沟槽和相应的有源区域的定义之后，提供栅极电极包括在与沟道相邻的部分处蚀刻隔离沟槽中的绝缘材料，使得沟道的一部分 未覆盖的具有脊形形状的部分包括顶侧和两个侧面，在顶侧和两个侧面提供栅极绝缘层，在栅极绝缘层上提供导电材料，从而使得栅电极 沿着通道的顶侧和两个横向侧面设置，其中蚀刻隔离沟槽中的绝缘材料，其中绝缘材料被局部蚀刻，其中绝缘槽的上部中的绝缘材料分离有效区域 互相维护。

公开(公告)号：US20070037340A1

公开(公告)日：2007-02-15

申请号：US11477577

申请日：2006-06-29

申请人： Albert Birner ,  Andreas Weber ,  Rolf Weis

发明人： Albert Birner ,  Andreas Weber ,  Rolf Weis

IPC分类号： H01L21/8238

CPC分类号： H01L21/76224 ,  H01L27/10873 ,  H01L29/1037

摘要： In a method for fabricating a semiconductor structure a semiconductor substrate comprising an active region with an uncovered top side is provided, at least one STI trench adjoining the active region is formed, and an STI divot is formed in the insulating filling. The at least one STI trench comprises an insulating filling extending to above the top side of the active region and the divot adjoins the active region and uncovers an edge of the uncovered top side of the active region. A hydrogen termination of the uncovered top side of the active region is formed and a heat treatment in a hydrogen atmosphere is carried out in order to form a rounding from the edge of the active region in such a way that the top side of the active region continuously merges into the STI divot.

摘要翻译： 在制造半导体结构的方法中，提供包括具有未覆盖的顶侧的有源区的半导体衬底，形成与有源区邻接的至少一个STI沟槽，并且在绝缘填充物中形成STI纹。 所述至少一个STI沟槽包括延伸到有源区的顶侧上方的绝缘填充物，并且所述突起邻接所述有源区，并且露出所述有源区的未覆盖的顶侧的边缘。 形成有源区的未覆盖的顶侧的氢终端，并且在氢气氛中进行热处理，以便从有源区的边缘形成圆化，使得有源区的顶侧 不断融入STI纹章。

公开(公告)号：US07067372B2

公开(公告)日：2006-06-27

申请号：US10657929

申请日：2003-09-09

申请人： Martin Schrems ,  Rolf Weis

发明人： Martin Schrems ,  Rolf Weis

IPC分类号： H01L21/8242

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10891

摘要： A memory cell has a trench, in which a trench capacitor is disposed. Furthermore a vertical transistor is formed in the trench above the trench capacitor. A barrier layer is disposed for the electric connection of the conductive trench filling to a lower doping region of the vertical transistor. The barrier layer is a diffusion barrier for dopants or impurities that are contained in the conductive trench filling.

摘要翻译： 存储单元具有沟槽，其中布置有沟槽电容器。 此外，在沟槽电容器上方的沟槽中形成垂直晶体管。 设置阻挡层用于将导电沟槽填充物与垂直晶体管的下掺杂区域的电连接。 阻挡层是包含在导电沟槽填充物中的掺杂剂或杂质的扩散阻挡层。

公开(公告)号：US06893938B2

公开(公告)日：2005-05-17

申请号：US10419588

申请日：2003-04-21

申请人： Munir D. Naeem ,  Hiroyuki Akatsu ,  Byeong Kim ,  Rolf Weis ,  David Mark Dobuzinksy ,  Johnathan E. Faltermeier

发明人： Munir D. Naeem ,  Hiroyuki Akatsu ,  Byeong Kim ,  Rolf Weis ,  David Mark Dobuzinksy ,  Johnathan E. Faltermeier

IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/3081

摘要： A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask is deposited over the first hard mask. The semiconductor wafer includes a first etching zone and at least a second etching zone disposed beneath the first etching zone. The etch process for the first etching zone and the etch process for the at least one second etching zone are selected such that smooth sidewall surface structures are formed within the semiconductor device. The etch processes for each subsequent etching zone may alternate between non-selective and selective etch processes to preserve at least the first hard mask material.

摘要翻译： 一种用于形成用于半导体器件的浅沟槽隔离（STI）的方法。 第一硬掩模沉积在半导体晶片上，并且第二硬掩模沉积在第一硬掩模上。 半导体晶片包括第一蚀刻区和设置在第一蚀刻区下方的至少第二蚀刻区。 选择用于第一蚀刻区域的蚀刻工艺和用于至少一个第二蚀刻区域的蚀刻工艺，使得在半导体器件内形成平滑的侧壁表面结构。 每个后续蚀刻区域的蚀刻工艺可以在非选择性和选择性蚀刻工艺之间交替，以至少保留第一硬掩模材料。