公开(公告)号：US20210159215A1

公开(公告)日：2021-05-27

申请号：US16694400

申请日：2019-11-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen WU ,  Peter RABKIN ,  Yangyin CHEN ,  Masaaki HIGASHITANI

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A bonded assembly includes a first die containing first bonding pads having sidewalls that are laterally bonded to sidewalls of second bonding pads of a second die.

公开(公告)号：US20210035965A1

公开(公告)日：2021-02-04

申请号：US17062988

申请日：2020-10-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuki MIZUTANI ,  Masaaki HIGASHITANI ,  James KAI

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  H01L27/11582 ,  H01L27/11556 ,  H01L25/00

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A source power supply network can be formed on the backside of the source layer.

公开(公告)号：US20210028148A1

公开(公告)日：2021-01-28

申请号：US16521849

申请日：2019-07-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen WU ,  Peter RABKIN ,  Yangyin CHEN ,  Masaaki HIGASHITANI

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768

Abstract: A bonded assembly includes a first semiconductor die including a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and contacting a respective first metal interconnect structure. Each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion. The bonded assembly includes a second semiconductor die attached to the first semiconductor die, and including a second substrate, second semiconductor devices located on the second substrate, second dielectric material layers located on the second semiconductor devices and embedding second metal interconnect structures, and bonding pad structures electrically connected to a respective one of the second metal interconnect structures and bonded to a respective first through-substrate via structure.

公开(公告)号：US20210005617A1

公开(公告)日：2021-01-07

申请号：US17031080

申请日：2020-09-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Murshed CHOWDHURY ,  Masaaki HIGASHITANI ,  Johann ALSMEIER

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and an array of memory opening fill structures extending through the alternating stack, an array of drain-select-level assemblies overlying the alternating stack and having a same two-dimensional periodicity as the array of memory opening fill structures, a first strip electrode portion laterally surrounding a first set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies, and a drain-select-level isolation strip including an isolation dielectric that contacts the first strip electrode portion and laterally spaced from the drain-select-level assemblies and extending between the first strip electrode portion and a second strip electrode portion.

公开(公告)号：US20200295039A1

公开(公告)日：2020-09-17

申请号：US16886081

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter RABKIN ,  Raghuveer S. MAKALA ,  Masaaki HIGASHITANI

IPC: H01L27/11582 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L27/11524 ,  H01L21/28

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing molybdenum portions located over a substrate, memory stack structures extending through the alternating stack, and including a memory film and a vertical semiconductor channel, and a backside blocking dielectric layer of a dielectric oxide material including aluminum atoms and at least one of lanthanum or zirconium atoms which directly contacts the molybdenum portions.

公开(公告)号：US20200251479A1

公开(公告)日：2020-08-06

申请号：US16408722

申请日：2019-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko SAKAKIBARA ,  Masaaki HIGASHITANI ,  Masanori TSUTSUMI ,  Zhixin CUI

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/285

Abstract: A three-dimensional memory device includes source-level material layers located over a substrate and including a lower semiconductor layer, a source contact layer, and an upper semiconductor layer. The lower semiconductor layer includes a first boron-doped semiconductor material, the upper semiconductor layer includes carbon doped second boron-doped semiconductor material, and the source contact layer includes a boron-doped semiconductor material. An alternating stack of insulating layers and electrically conductive layers is located over the source-level material layers. Memory stack structures vertically extend through the alternating stack, the upper semiconductor layer, and the source contact layer. Each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel that contacts the source contact layer. Carbon atoms in the upper semiconductor layer and optionally the lower semiconductor layer suppress diffusion of boron atoms into the vertical semiconductor channel.

公开(公告)号：US20170373087A1

公开(公告)日：2017-12-28

申请号：US15195377

申请日：2016-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitoshi ITO ,  Masaaki HIGASHITANI ,  Cheng-Chung CHU ,  Jayavel PACHAMUTHU ,  Tuan PHAM

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0649

Abstract: Die cracking of a three dimensional memory device may be reduced by adding offsets to backside contact via structures. Each backside contact via structure can include laterally extending portions that extend along a first horizontal direction adjoined by adjoining portions that extend along a horizontal direction other than the first horizontal direction. In order to preserve periodicity of memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers, the distance between an outermost row of a string of memory stack structures between a pair of backside contact via structures and a most proximal backside contact via structure can vary from a laterally extending portion to another laterally extending portion within the most proximal backside contact via structure. Source shunt lines that are parallel to bit lines can be formed over a selected subset of offset portions of the backside contact via structures.

公开(公告)号：US20170373078A1

公开(公告)日：2017-12-28

申请号：US15195446

申请日：2016-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Cheng-Chung CHU ,  Jayavel PACHAMUTHU ,  Tuan PHAM ,  Fumitoshi ITO ,  Masaaki HIGASHITANI

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/22 ,  H01L27/11519 ,  H01L23/522 ,  H01L21/768 ,  H01L29/417 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three-dimensional memory device includes a plurality of planes, each having a respective alternating stack, strings of memory stack structures which extends through the respective alternating stack, and backside contact via structures vertically extending through the respective alternating stack, extending generally along the first horizontal direction, and laterally separating neighboring pairs of strings of memory stack structures along a second horizontal direction. A first plane includes a first plurality of strings that are laterally spaced apart along the second horizontal direction by a first plurality of backside contact via structures. A second plane laterally shifted from the first plane along the first horizontal direction and including a second plurality of strings that are laterally spaced apart along the second horizontal direction by a second plurality of backside contact via structures which are laterally offset with respect the first plurality of backside contact via structures along the second horizontal direction.