公开(公告)号：US20190043830A1

公开(公告)日：2019-02-07

申请号：US15669243

申请日：2017-08-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko SAKAKIBARA ,  Satoshi SHIMIZU ,  Naoto NORIZUKI

IPC: H01L25/065 ,  H05K7/02 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11568 ,  H01L49/02

Abstract: A three-dimensional memory device includes a p-doped source semiconductor layer located over a substrate, a p-doped strap semiconductor layer located over the p-doped source semiconductor layer, an alternating stack of electrically conductive layers and insulating layers located over the p-doped strap semiconductor layer, and memory stack structures that extend through the alternating stack and into an upper portion of the p-doped source semiconductor layer. Each memory stack structure includes a p-doped vertical semiconductor channel and a memory film laterally surrounding the p-doped vertical semiconductor channel. A top surface of each p-doped vertical semiconductor channel contacts a bottom surface of a respective n-doped region. A sidewall of a bottom portion of each p-doped vertical semiconductor channel contacts a respective sidewall of the p-doped strap semiconductor layer.

公开(公告)号：US20200303397A1

公开(公告)日：2020-09-24

申请号：US16361722

申请日：2019-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin CUI ,  Kiyohiko SAKAKIBARA ,  Yanli ZHANG

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, drain-select-level trenches that vertically extend through at least one drain-select-level electrically conductive layer and laterally extend along a first horizontal direction and divide each drain-select-level electrically conductive layer into multiple drain-select-level electrically conductive strips, and pairs of vertical conductive strips located within a respective one of the drain-select-level trenches. Each of the vertical conductive strips has a pair of vertical straight sidewalls that laterally extends along the first horizontal direction. Each drain-select-level electrode may have at least one drain-select-level electrically conductive layer and at least one vertical conductive strip.

公开(公告)号：US20170278859A1

公开(公告)日：2017-09-28

申请号：US15250185

申请日：2016-08-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Fei ZHOU ,  Somesh PERI ,  Masanori TSUTSUMI ,  Keerti SHUKLA ,  Yusuke IKAWA ,  Kiyohiko SAKAKIBARA ,  Eisuke TAKII

IPC: H01L27/115 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02326 ,  H01L21/31111 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop material portions are provided at each level of the sacrificial material layers around the memory opening. The annular etch stop material portions can be formed by conversion of surface portions of the sacrificial material layers into dielectric material portion, or by recessing the sacrificial material layers around the memory opening and filling indentations around the memory opening. After formation of a memory stack structure, the sacrificial material layers are removed from the backside. The annular etch stop material portions are at least partially converted to form charge trapping material portions. Vertical isolation of the charge trapping material portions among one another around the memory stack structure minimizes leakage between the charge trapping material portions located at different word line levels.

公开(公告)号：US20200279866A1

公开(公告)日：2020-09-03

申请号：US16876395

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi NISHIKAWA ,  Kiyohiko SAKAKIBARA

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches which laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction, and memory stack structures arranged in rows extending along the first horizontal direction. Each row of memory stack structures is located on a respective sidewall of the line trenches. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric contacting the vertical semiconductor channel, a charge storage layer contacting the tunneling dielectric, and a composite blocking dielectric. The composite blocking dielectric includes a first dipole-containing blocking dielectric layer stack, a homogeneous blocking dielectric layer, and a second dipole-containing blocking dielectric layer stack.

公开(公告)号：US20200251479A1

公开(公告)日：2020-08-06

申请号：US16408722

申请日：2019-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko SAKAKIBARA ,  Masaaki HIGASHITANI ,  Masanori TSUTSUMI ,  Zhixin CUI

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/285

Abstract: A three-dimensional memory device includes source-level material layers located over a substrate and including a lower semiconductor layer, a source contact layer, and an upper semiconductor layer. The lower semiconductor layer includes a first boron-doped semiconductor material, the upper semiconductor layer includes carbon doped second boron-doped semiconductor material, and the source contact layer includes a boron-doped semiconductor material. An alternating stack of insulating layers and electrically conductive layers is located over the source-level material layers. Memory stack structures vertically extend through the alternating stack, the upper semiconductor layer, and the source contact layer. Each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel that contacts the source contact layer. Carbon atoms in the upper semiconductor layer and optionally the lower semiconductor layer suppress diffusion of boron atoms into the vertical semiconductor channel.

公开(公告)号：US20190067025A1

公开(公告)日：2019-02-28

申请号：US15685254

申请日：2017-08-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shinsuke YADA ,  Akihisa SAI ,  Kiyohiko SAKAKIBARA

IPC: H01L21/306 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11529 ,  H01L21/28 ,  H01L21/768 ,  G11C16/26 ,  G11C8/14 ,  H01L23/528

CPC classification number: H01L21/30608 ,  G11C8/14 ,  G11C16/26 ,  H01L21/28 ,  H01L21/76802 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11582

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layers are formed as, or are replaced with, electrically conductive layers. An insulating cap layer is formed over the alternating stack. After formation of memory stack structures through each layer of the alternating stack and the insulating cap layer, a line trench straddling a neighboring pair of rows of the memory stack is formed. Sidewalls of the line trench include a sidewall of each memory stack structure within the neighboring pair of rows of the memory stack structures. A drain select gate dielectric and a drain select electrode line are formed within the line trench. The drain select electrode line controls flow of electrical current through an upper portion of a vertical semiconductor channel within each memory stack structure below the drain regions to activate or deactivate the neighboring rows.

公开(公告)号：US20170025421A1

公开(公告)日：2017-01-26

申请号：US15284067

申请日：2016-10-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko SAKAKIBARA ,  Yusuke IKAWA

IPC: H01L27/115 ,  G11C16/04 ,  H01L29/10 ,  H01L29/06 ,  H01L29/04 ,  H01L29/08

CPC classification number: H01L27/115 ,  G11C16/0483 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/7391 ,  H01L29/868

Abstract: Data stored in a plurality of charge storage elements in a three-dimensional memory device can be read with high speed by measuring a majority charge carrier current passing through a vertical semiconductor channel. A memory film is provided in a memory opening extending through an alternating stack of insulating layers and electrically conductive layers. A set of doped semiconductor material regions having a doping of a first conductivity type can collectively extend continuously from underneath a top surface of a substrate through the memory film to a level of a topmost layer of the alternating stack. A well contact via structure can contact a doped contact region, which is an element of the set of doped semiconductor material regions. A p-n junction is provided within each memory opening between the doped vertical semiconductor channel and an upper doped semiconductor region having a doping of a second conductivity type.

Abstract translation: 通过测量通过垂直半导体通道的多数载流子电流，可以高速读取存储在三维存储器件中的多个电荷存储元件中的数据。 记忆膜设置在延伸穿过交替堆叠的绝缘层和导电层的存储器开口中。 具有第一导电类型的掺杂的一组掺杂半导体材料区域可以从衬底的顶表面下方连续地延伸通过存储膜到交替堆叠的最上层的水平。 阱接触通孔结构可以接触作为该掺杂半导体材料区域的元素的掺杂接触区域。 在掺杂的垂直半导体沟道和具有第二导电类型的掺杂的上掺杂半导体区之间的每个存储器开口内提供p-n结。

公开(公告)号：US20200098780A1

公开(公告)日：2020-03-26

申请号：US16138001

申请日：2018-09-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin CUI ,  Kiyohiko SAKAKIBARA ,  Shinsuke YADA

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/423

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, drain-select-level gate electrodes located over the alternating stack, memory openings extending through the alternating stack and a respective one of the drain-select-level gate electrodes, and memory opening fill structures located in the memory openings. The memory opening fill structures can have a stepped profile to provide a smaller lateral dimension at the level of the drain-select-level gate electrodes than within the alternating stack. Each of the drain-select-level gate electrodes includes a planar portion having two sets of vertical sidewall segments, and a set of cylindrical portions vertically protruding upward from the planar portion and laterally surrounding a respective one of the memory opening fill structures. The memory opening fill structures can be formed on-pitch as a two-dimensional array.

公开(公告)号：US20200058672A1

公开(公告)日：2020-02-20

申请号：US16136652

申请日：2018-09-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi NISHIKAWA ,  Kiyohiko SAKAKIBARA

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches which laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction, and memory stack structures arranged in rows extending along the first horizontal direction. Each row of memory stack structures is located on a respective sidewall of the line trenches. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric contacting the vertical semiconductor channel, a charge storage layer contacting the tunneling dielectric, and a composite blocking dielectric. The composite blocking dielectric includes a first dipole-containing blocking dielectric layer stack, a homogeneous blocking dielectric layer, and a second dipole-containing blocking dielectric layer stack.