公开(公告)号：US11855120B2

公开(公告)日：2023-12-26

申请号：US17649982

申请日：2022-02-04

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot ,  Christelle Michau

IPC: H01L27/146 ,  H01L21/762

CPC classification number: H01L27/14685 ,  H01L21/76254 ,  H01L27/14625

Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 μm is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.

公开(公告)号：US20230386896A1

公开(公告)日：2023-11-30

申请号：US18449298

申请日：2023-08-14

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Guillaume Chabanne ,  Nicolas Daval

IPC: H01L21/762

CPC classification number: H01L21/76275 ,  H01L21/76254

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer. After transferring the monocrystalline semiconductor layer and before the cutting operation, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.

公开(公告)号：US20230317496A1

公开(公告)日：2023-10-05

申请号：US18004156

申请日：2021-03-30

Applicant: Soitec

Inventor： Isabelle Bertrand ,  Frédéric Alibert ,  Romain Bouveyron ,  Walter Schwarzenbach

IPC: H01L21/683 ,  H01L21/324 ,  H01L27/12

CPC classification number: H01L21/6835 ,  H01L21/324 ,  H01L27/1203

Abstract: A carrier substrate comprises monocrystalline silicon, and has a front face and a back face. The carrier substrate comprises:



a surface region extending from the front face to a depth of between 800 nm and 2 microns, having less than 10 crystal-originated particles (COPs) (as detected by inspecting the surface using dark-field reflection microscopy);
an upper region extending from the front face to a depth of between a few microns and 40 microns and having an interstitial oxygen (Oi) content less than or equal to 7.5E17 Oi/cm3 and a resistivity higher than 500 ohm·cm, and
a lower region extending between the upper region and the back face and having a micro-defect (BMD) concentration greater than or equal to 1E8/cm3.




A method is used to manufacture such a carrier substrate.

公开(公告)号：US20230215760A1

公开(公告)日：2023-07-06

申请号：US17998894

申请日：2021-05-18

Applicant: Soitec

Inventor： Isabelle Bertrand ,  Walter Schwarzenbach ,  Frédéric Allibert

IPC: H01L21/762

CPC classification number: H01L21/76254

Abstract: A method for manufacturing a semiconductor-on-insulator substrate for radiofrequency applications, comprises: providing a P-doped semiconductor donor substrate; forming a sacrificial layer on the donor substrate; implanting atomic species through the sacrificial layer so as to form in the donor substrate an area of embrittlement defining a thin semiconductor layer that is to be transferred; removing the sacrificial layer from the donor substrate after the implantation; providing a supporting semiconductor substrate having an electrical resistivity greater than or equal to 500 Ω·cm; forming an electrically insulating layer on the supporting substrate; bonding the donor substrate on the supporting substrate, the thin semiconductor layer and the electrically insulating layer being at the interface of the bonding; detaching the donor substrate along the area of embrittlement so as to transfer the thin semiconductor layer from the donor substrate onto the supporting substrate.

公开(公告)号：US20230039295A1

公开(公告)日：2023-02-09

申请号：US17758848

申请日：2021-01-14

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  David Herisson ,  Alain Delpy

IPC: H01L27/146

Abstract: A method for fabricating an image sensor, comprising: providing a receiver substrate comprising a base substrate and an active layer comprising pixels, each pixel comprising a doped region for collecting the electric charges generated in the pixel, the receiver substrate being devoid of metal interconnections, providing a donor substrate comprising a weakened zone limiting a monocrystalline semiconductor layer, bonding the donor substrate to the receiver substrate, detaching the donor substrate along the weakened zone, so as to transfer the semiconductor layer to the receiver substrate, implementing a finishing treatment on the transferred monocrystalline semiconductor layer, the finishing treatment comprising (i) thinning of the transferred monocrystalline semiconductor layer by sacrificial oxidation followed by chemical etching and (ii) smoothing of the transferred monocrystalline semiconductor layer by means of at least one rapid anneal.

公开(公告)号：US20220399441A1

公开(公告)日：2022-12-15

申请号：US17347417

申请日：2021-06-14

Applicant: Soitec ,  National University of Singapore

Inventor： Bich-Yen Nguyen ,  Christophe Maleville ,  Walter Schwarzenbach ,  Gong Xiao ,  Aaron Thean ,  Chen Sun ,  Haiwen Xu

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/161 ,  H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L21/84

Abstract: A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about −0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon on insulator device.

公开(公告)号：US20220059603A1

公开(公告)日：2022-02-24

申请号：US17418148

申请日：2019-12-23

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Damien Massy ,  Nadia Ben Mohamed ,  Nicolas Daval ,  Christophe Girard ,  Christophe Maleville

IPC: H01L27/146 ,  H01L31/18

Abstract: A method of manufacturing a substrate for a front-facing image sensor, comprises:—providing a donor substrate comprising a semiconductor layer to be transferred,—providing a semiconductor carrier substrate,—bonding the donor substrate to the carrier substrate, an electrically insulating layer being at the bonding interface,—transferring the semiconductor layer to the carrier substrate,—implanting gaseous ions in the carrier substrate via the transferred semiconductor layer and the electrically insulating layer, and—after the implantation, epitaxially growing an additional semiconductor layer on the transferred semiconductor layer.

公开(公告)号：US20160086803A1

公开(公告)日：2016-03-24

申请号：US14934567

申请日：2015-11-06

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Christophe Maleville

IPC: H01L21/225 ,  H01L21/762 ,  H01L29/10 ,  H01L21/84

CPC classification number: H01L21/2253 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02617 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/76251 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/32 ,  H01L29/7849

Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.

Abstract translation: 制造半导体结构的方法包括提供包括基底基板，在基底基板上方的应变应力层，表面半导体层和应力层与表面半导体层之间的电介质层的绝缘体上半导体 。 离子被注入或穿过应力层的第一区域，并且在应力层的第一区域上方的表面半导体层上形成附加的半导体材料。 在应力层的第一区域上方的表面半导体层的第一区域中的应变状态被改变，并且沟槽结构至少部分地形成到基底衬底中。 在应力层的第二区域上方的表面半导体层的第二区域中改变应变状态。 使用这种方法制造半导体结构。

公开(公告)号：US20150118764A1

公开(公告)日：2015-04-30

申请号：US14397287

申请日：2013-05-01

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Carine Duret ,  Francois Boedt

IPC: H01L21/306 ,  H01L21/762 ,  H01L21/66

CPC classification number: H01L21/30604 ,  H01L21/76251 ,  H01L22/12 ,  H01L22/20

Abstract: The invention relates to a process for treating a structure of semiconductor-on-insulator type successively comprising a support substrate, a dielectric layer and a semiconductor layer having a thickness of less than or equal to 100 nm, the semiconductor layer being covered with a sacrificial oxide layer, comprising: measuring, at a plurality of points distributed over the surface of the structure, the thickness of the sacrificial oxide layer and of the semiconductor layer, so as to produce a mapping of the thickness of the semiconductor layer and to determine, from the measurements, the average thickness of the semiconductor layer, selective etching of the sacrificial oxide layer so as to expose the semiconductor layer, and carrying out a chemical etching of the semiconductor layer, the application, temperature and/or duration conditions of which are adjusted as a function of the mapping and/or of the mean thickness of the semiconductor layer, so as to thin, at least locally, the semiconductor layer by a thickness identified as being an overthickness at the end of the measurement step.

Abstract translation: 本发明涉及一种用于处理绝缘体上半导体结构的方法，该方法连续地包括一个具有小于或等于100nm的厚度的支撑衬底，电介质层和半导体层，半导体层被牺牲 氧化物层，包括：在分布在结构表面上的多个点处测量牺牲氧化物层和半导体层的厚度，以便产生半导体层的厚度的映射， 从测量中，半导体层的平均厚度，牺牲氧化物层的选择性蚀刻以暴露半导体层，并且对半导体层进行化学蚀刻，其应用，温度和/或持续时间条件是 作为半导体层的平均厚度和/或半导体层的平均厚度的函数进行调整，以至少局部地使半 导体层在测量步骤结束时被认为是厚厚的厚度。