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    Method for Reading an EEPROM and Corresponding Device
    51.
    发明申请
    Method for Reading an EEPROM and Corresponding Device 审中-公开

    公开(公告)号：US20170323684A1

    公开(公告)日：2017-11-09

    申请号：US15659891

    申请日：2017-07-26

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista ,  Victorien Brecte

    IPC: G11C16/26 ,  G11C16/24 ,  G11C16/04

    CPC classification number: G11C16/26 ,  G11C7/067 ,  G11C16/0433 ,  G11C16/24

    Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.

    Memory device including a SRAM memory plane and a non volatile memory plane, and operating methods
    55.
    发明授权
    Memory device including a SRAM memory plane and a non volatile memory plane, and operating methods 有权
    存储器件包括SRAM存储器平面和非易失性存储器平面以及操作方法

    公开(公告)号：US09245624B2

    公开(公告)日：2016-01-26

    申请号：US14298264

    申请日：2014-06-06

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista

    IPC: G11C14/00 ,  G11C16/10

    CPC classification number: G11C14/0063 ,  G11C16/10

    Abstract: A memory device includes at least one memory cell having a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise and two groups, each having at least one non-volatile elementary memory cell. The non-volatile elementary memory cells of the two groups are coupled firstly to a supply terminal and secondly to the outputs and to the inputs of the two inverters via a controllable interconnection stage.

    Abstract translation: 存储器件包括至少一个具有第一SRAM型元件存储器单元的存储器单元，所述第一SRAM型元件存储器单元具有彼此交叉耦合的两个反相器和两组，每个具有至少一个非易失性基本存储器单元。 两组的非易失性基本存储单元首先通过可控制的互连级耦合到电源端子，其次耦合到两个反相器的输出端和输入端。

    Integrated Structure Comprising Neighboring Transistors
    56.
    发明申请
    Integrated Structure Comprising Neighboring Transistors 有权
    包含相邻晶体管的集成结构

    公开(公告)号：US20150270002A1

    公开(公告)日：2015-09-24

    申请号：US14657963

    申请日：2015-03-13

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Marc Battista ,  François Tailliet

    IPC: G11C16/04 ,  H01L29/49 ,  H01L27/088 ,  H01L29/51 ,  G11C16/08 ,  G11C11/418

    CPC classification number: H01L27/1104 ,  G11C11/4125 ,  G11C11/418 ,  G11C14/0063 ,  G11C16/045 ,  G11C16/08 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4916 ,  H01L29/513

    Abstract: An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.

    Abstract translation: 集成结构包括具有覆盖第一栅极电介质的第一可控栅极区域和与第一MOS晶体管相邻并且具有覆盖第一栅极电介质的第二可控栅极区域的第一MOS晶体管的第一MOS晶体管。 公共导电区域覆盖第一和第二栅极区域并且由第二栅极电介质分离。 公共导电区域包括位于第一和第二栅极区域的一部分上的连续元件以及从连续元件向衬底延伸至第一栅极电介质的分支。 位于第一和第二栅极区之间的分支。

    Method for Managing the Operation of a Memory Device Having a SRAM Memory Plane and a Non Volatile Memory Plane, and Corresponding Memory Device
    57.
    发明申请
    Method for Managing the Operation of a Memory Device Having a SRAM Memory Plane and a Non Volatile Memory Plane, and Corresponding Memory Device 有权
    用于管理具有SRAM存储器平面和非易失性存储器平面的存储器件的操作的方法以及对应的存储器件

    公开(公告)号：US20150016188A1

    公开(公告)日：2015-01-15

    申请号：US14315401

    申请日：2014-06-26

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet ,  Marc Battista

    IPC: G11C14/00

    CPC classification number: G11C14/0063 ,  G11C7/1006 ,  G11C16/0408 ,  G11C16/3418

    Abstract: A method can be used for managing the operation of a memory cell that includes an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another. A data bit is transferred between the SRAM elementary memory cell and the non-volatile elementary memory cell. A control datum is stored in a control memory cell that is functionally analogous to and associated with the memory cell. The data bit is read from the SRAM elementary memory cell and a corresponding read of the control datum is performed. The data bit read from the SRAM elementary memory cell is inverted if the control datum has a first value but the data bit read from the SRAM elementary memory cell is not inverted if the control datum has a second value.

    Abstract translation: 一种方法可用于管理包括彼此耦合的SRAM基本存储单元和非易失性基本存储单元的存储单元的操作。 数据位在SRAM单元存储单元和非易失性单元存储单元之间传送。 控制数据被存储在功能上类似于存储器单元并与其相关联的控制存储器单元中。 从SRAM基本存储单元读取数据位，并执行相应的控制数据读取。 如果控制数据具有第一值，则从SRAM基本存储器单元读取的数据位被反转，但是如果控制数据具有第二值，则从SRAM基本存储单元读取的数据位不反转。

    Electrostatic discharge protection device
    59.
    发明授权
    Electrostatic discharge protection device 有权

    公开(公告)号：US11811221B2

    公开(公告)日：2023-11-07

    申请号：US17643530

    申请日：2021-12-09

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet

    IPC: H02H9/04

    CPC classification number: H02H9/04

    Abstract: The present description concerns an electrostatic discharge protection device including a first clipping circuit coupled between a first node and a second node and a second active clipping circuit, series-coupled with a first resistor, the second clipping circuit and the first resistor being coupled between the first and second nodes, the second clipping circuit including a field-effect transistor having a metal-oxide-semiconductor structure.

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