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    Voltage level shifter cell and integrated circuit including the same
    52.
    发明授权
    Voltage level shifter cell and integrated circuit including the same 有权

    公开(公告)号：US11728795B2

    公开(公告)日：2023-08-15

    申请号：US17564915

    申请日：2021-12-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chanhee Park ,  Ahreum Kim ,  Minsu Kim

    IPC: H03K19/0175 ,  H03K3/356 ,  H01L27/02 ,  G06F30/30

    CPC classification number: H03K3/356113 ,  G06F30/30 ,  H01L27/0207 ,  H03K19/0175

    Abstract: A voltage level shifter cell, which is configured to convert voltage levels of input signals of multi-bits, includes: a first circuit area including a first voltage level shifter configured to convert a 1-bit first input signal from among the input signals; and a second circuit area including a second voltage level shifter configured to convert a 1-bit second input signal from among the input signals, wherein the first circuit area and the second circuit area share a first N-well to which a first power voltage is applied, and the first circuit area and the second circuit area share a second N-well to which a second power voltage is applied, wherein the first N-well is formed to extend in a first direction, and the first N-well and the second N-well are arranged to overlap in a second direction crossing the first direction.

    MEMORY DEVICE FOR COLUMN REPAIR
    55.
    发明公开
    MEMORY DEVICE FOR COLUMN REPAIR 审中-公开

    公开(公告)号：US20230154559A1

    公开(公告)日：2023-05-18

    申请号：US18149302

    申请日：2023-01-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jooyong PARK ,  Minsu Kim ,  Daeseok Byeon ,  Pansuk Kwak

    IPC: G11C29/00 ,  G11C16/04 ,  G11C29/44 ,  G06F11/20

    CPC classification number: G11C29/838 ,  G11C16/0483 ,  G11C29/44 ,  G06F11/2094 ,  G11C2029/1204

    Abstract: A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

    Memory device skipping refresh operation and operation method thereof
    56.
    发明授权
    Memory device skipping refresh operation and operation method thereof 有权

    公开(公告)号：US11610624B2

    公开(公告)日：2023-03-21

    申请号：US17474666

    申请日：2021-09-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

    IPC: G11C11/406

    Abstract: Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.

    Memory device for column repair
    57.
    发明授权
    Memory device for column repair 有权

    公开(公告)号：US11574700B2

    公开(公告)日：2023-02-07

    申请号：US17245568

    申请日：2021-04-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jooyong Park ,  Minsu Kim ,  Daeseok Byeon ,  Pansuk Kwak

    IPC: G11C29/00 ,  G06F11/20 ,  G11C16/04 ,  G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/12 ,  G11C29/02 ,  G11C29/52 ,  G11C29/42 ,  G11C29/24

    Abstract: A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

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