公开(公告)号：US20130200366A1

公开(公告)日：2013-08-08

申请号：US13751753

申请日：2013-01-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Hiroyuki MIYAKE ,  Kouhei TOYOTAKA

IPC: H01L29/786

CPC classification number: H01L29/78693 ,  H01L29/41733 ,  H01L29/7869

Abstract: To provide a highly reliable semiconductor device in which a transistor including an oxide semiconductor film has stable electric characteristics. The semiconductor device includes a gate electrode layer over a substrate, a gate insulating film over the gate electrode layer, an oxide semiconductor film over the gate insulating film, a drain electrode layer which is over the oxide semiconductor film so as to overlap with the gate electrode layer, and a source electrode layer provided so as to cover part of an outer edge portion of the oxide semiconductor film. An outer edge portion of the drain electrode layer is on an inner side than an outer edge portion of the gate electrode layer.

Abstract translation: 为了提供一种高可靠性的半导体器件，其中包括氧化物半导体膜的晶体管具有稳定的电特性。 半导体器件包括在基板上的栅极电极层，栅极电极层上的栅极绝缘膜，栅极绝缘膜上的氧化物半导体膜，位于氧化物半导体膜上方以与栅极重叠的漏极层 电极层和设置为覆盖氧化物半导体膜的外缘部的一部分的源电极层。 漏电极层的外缘部位于比栅电极层的外缘部更内侧。

公开(公告)号：US20130168670A1

公开(公告)日：2013-07-04

申请号：US13777106

申请日：2013-02-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO.,LTD.

Inventor： Seiko INOUE ,  Hiroyuki MIYAKE ,  Kouhei TOYOTAKA

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1251

Abstract: A semiconductor device including a first gate electrode and a second gate electrode formed apart from each other over an insulating surface, an oxide semiconductor film including a region overlapping with the first gate electrode with a gate insulating film interposed therebetween, a region overlapping with the second gate electrode with the gate insulating film interposed therebetween, and a region overlapping with neither the first gate electrode nor the second gate electrode, and an insulating film covering the gate insulating film, the first gate electrode, the second gate electrode, and the oxide semiconductor film, and being in direct contact with the oxide semiconductor film is provided.

Abstract translation: 一种半导体器件，包括在绝缘表面上彼此分开形成的第一栅电极和第二栅电极，包括与第一栅极重叠的区域的氧化物半导体膜，其间插入有栅极绝缘膜，与第二栅极重叠的区域 栅极电极，其间插入有栅极绝缘膜，以及与第一栅极电极和第二栅极电极都不重叠的区域，以及覆盖栅极绝缘膜，第一栅极电极，第二栅极电极和氧化物半导体的绝缘膜 膜，并且与氧化物半导体膜直接接触。

公开(公告)号：US20250142973A1

公开(公告)日：2025-05-01

申请号：US19010328

申请日：2025-01-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kouhei TOYOTAKA ,  Jun KOYAMA ,  Hiroyuki MIYAKE

IPC: H10D86/60 ,  G02F1/1334 ,  G02F1/1337 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/20 ,  G09G3/3233 ,  G09G3/3258 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/36 ,  G11C19/28 ,  H10D30/67 ,  H10D86/40

Abstract: A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

公开(公告)号：US20250120181A1

公开(公告)日：2025-04-10

申请号：US18982263

申请日：2024-12-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka SHIONOIRI ,  Hiroyuki MIYAKE ,  Kiyoshi KATO

IPC: H10D86/80 ,  G11C16/04 ,  H10B41/70 ,  H10B69/00 ,  H10D30/67 ,  H10D86/40 ,  H10D86/60

Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

公开(公告)号：US20250098315A1

公开(公告)日：2025-03-20

申请号：US18897319

申请日：2024-09-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroyuki MIYAKE

IPC: H01L27/12 ,  G09G3/3233 ,  G09G3/3275 ,  H01L27/06 ,  H01L33/62 ,  H10K59/10

Abstract: An object is to prevent an operation defect and to reduce an influence of fluctuation in threshold voltage of a field-effect transistor. A field-effect transistor, a switch, and a capacitor are provided. The field-effect transistor includes a first gate and a second gate which overlap with each other with a channel formation region therebetween, and the threshold voltage of the field-effect transistor varies depending on the potential of the second gate. The switch has a function of determining whether electrical connection between one of a source and a drain of the field-effect transistor and the second gate of the field-effect transistor is established. The capacitor has a function of holding a voltage between the second gate of the field-effect transistor and the other of the source and the drain of the field-effect transistor.

公开(公告)号：US20250076932A1

公开(公告)日：2025-03-06

申请号：US18905374

申请日：2024-10-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiharu HIRAKATA ,  Hiroyuki MIYAKE ,  Seiko INOUE ,  Shunpei YAMAZAKI

IPC: G06F1/16 ,  G06F3/041

Abstract: A display device with low power consumption is provided. Furthermore, a display device in which an image is displayed in a region that can be used in a folded state is provided. The conceived display device includes a display portion that can be opened and folded, a sensing portion that senses a folded state of the display portion, and an image processing portion that generates, when the display portion is in the folded state, an image in which a black image is displayed in part of the display portion.

公开(公告)号：US20250076712A1

公开(公告)日：2025-03-06

申请号：US18936635

申请日：2024-11-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Ryo HATSUMI ,  Daisuke KUBOTA ,  Hiroyuki MIYAKE

IPC: G02F1/1343 ,  G02F1/1333 ,  G02F1/1337 ,  G02F1/1362

Abstract: A display device with less light leakage and excellent contrast is provided. A display device having a high aperture ratio and including a large-capacitance capacitor is provided. A display device in which wiring delay due to parasitic capacitance is reduced is provided. A display device includes a transistor over a substrate, a pixel electrode connected to the transistor, a signal line electrically connected to the transistor, a scan line electrically connected to the transistor and intersecting with the signal line, and a common electrode overlapping with the pixel electrode and the signal line with an insulating film provided therebetween. The common electrode includes stripe regions extending in a direction intersecting with the signal line.

公开(公告)号：US20250020960A1

公开(公告)日：2025-01-16

申请号：US18896991

申请日：2024-09-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroyuki MIYAKE ,  Makoto KANEYASU

IPC: G02F1/1343 ,  G02F1/13357 ,  G02F1/136 ,  G02F1/1362 ,  G09F9/30 ,  G09G3/36 ,  H01L27/12 ,  H01L29/786

Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film. The signal line intersects with the scan line, the first electrode is electrically connected to the signal line, the first electrode has a region overlapping with the scan line, the second electrode faces the first electrode, the third electrode faces the first electrode, the first pixel electrode is electrically connected to the second electrode, the second pixel electrode is electrically connected to the third electrode, the semiconductor film is in contact with the first electrode, the second electrode, and the third electrode, and the semiconductor film is provided between the scan line and the first electrode to the third electrode.

公开(公告)号：US20240243204A1

公开(公告)日：2024-07-18

申请号：US18522543

申请日：2023-11-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hiroyuki MIYAKE ,  Kei TAKAHASHI ,  Kouhei TOYOTAKA ,  Masashi TSUBUKU ,  Kosei NODA ,  Hideaki KUWABARA

IPC: H01L29/786 ,  G06K19/077 ,  H01L21/8236 ,  H01L23/66 ,  H01L27/088 ,  H01L27/12 ,  H01L29/24 ,  H01L29/26 ,  H01L29/66 ,  G11C7/00 ,  G11C19/28 ,  H02M3/07

CPC classification number: H01L29/78609 ,  G06K19/07758 ,  H01L21/8236 ,  H01L23/66 ,  H01L27/0883 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/26 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  G11C7/00 ,  G11C19/28 ,  H01L2223/6677 ,  H02M3/07

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor, With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

公开(公告)号：US20240203337A1

公开(公告)日：2024-06-20

申请号：US18591443

申请日：2024-02-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hiroyuki MIYAKE

IPC: G09G3/3208 ,  G09G3/20 ,  G09G3/3233 ,  H01L27/12 ,  H01L29/786 ,  H10K59/121 ,  H10K59/131

CPC classification number: G09G3/3208 ,  G09G3/2003 ,  G09G3/3233 ,  H01L27/1225 ,  H01L29/78609 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H10K59/1213 ,  H10K59/131 ,  G09G2330/021

Abstract: Objects are to provide a display device the power consumption of which is reduced, to provide a self-luminous display device the power consumption of which is reduced and which is capable of long-term use in a dark place. A circuit is formed using a thin film transistor in which a highly-purified oxide semiconductor is used and a pixel can keep a certain state (a state in which a video signal has been written). As a result, even in the case of displaying a still image, stable operation is easily performed. In addition, an operation interval of a driver circuit can be extended, which results in a reduction in power consumption of a display device. Moreover, a light-storing material is used in a pixel portion of a self-luminous display device to store light, whereby the display device can be used in a dark place for a long time.