公开(公告)号：US20130320333A1

公开(公告)日：2013-12-05

申请号：US13898716

申请日：2013-05-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Shunpei YAMAZAKI

IPC: H01L27/146

CPC classification number: G06F3/042 ,  G02F1/13338 ,  H01L27/1446 ,  H01L27/1461 ,  H01L27/14641 ,  H01L27/14678 ,  H01L31/105

Abstract: In a display portion of a liquid crystal display device, the dead space corresponding to a unit pixel is reduced while the aperture ratio of the unit pixel is increased. One amplifier circuit portion is shared by a plurality of unit pixels, so that the area of the amplifier circuit portion corresponding to the unit pixel is reduced and the aperture ratio of the unit pixel is increased. In addition, when the amplifier circuit portion is shared by a larger number of unit pixels, a photosensor circuit corresponding to the unit pixel can be prevented from increasing in area even with an increase in photosensitivity. Furthermore, an increase in the aperture ratio of the unit pixel results in a reduction in the power consumption of a backlight in a liquid crystal display device.

公开(公告)号：US20130314346A1

公开(公告)日：2013-11-28

申请号：US13864752

申请日：2013-04-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Yasuyuki ARAI ,  Ikuko KAWAMATA ,  Atsushi MIYAGUCHI ,  Yoshitaka MORIYA

IPC: G09G5/00

CPC classification number: G06F1/1652 ,  G02F1/133305 ,  G02F1/13452 ,  G02F1/1368 ,  G06F1/1616 ,  G06F1/1635 ,  G06F1/1643 ,  G06F1/1647 ,  G06F3/1423 ,  G06F3/147 ,  G09G3/20 ,  G09G3/2096 ,  G09G3/3225 ,  G09G3/344 ,  G09G3/3648 ,  G09G5/003 ,  G09G2300/08 ,  G09G2310/0218 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0281 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2360/144 ,  G09G2380/02 ,  G09G2380/14

Abstract: An e-book reader in which destruction of a driver circuit at the time when a flexible panel is handled is inhibited. In addition, an e-book reader having a simplified structure. A plurality of flexible display panels each including a display portion in which display control is performed by a scan line driver circuit and a signal line driver circuit, and a binding portion fastening the plurality of display panels together are included. The signal line driver circuit is provided inside the binding portion, and the scan line driver circuit is provided at the edge of the display panel in a direction perpendicular to the binding portion.

公开(公告)号：US20130294481A1

公开(公告)日：2013-11-07

申请号：US13873550

申请日：2013-04-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Jun KOYAMA ,  Shunpei YAMAZAKI

IPC: G01K7/01

CPC classification number: G01K7/01

Abstract: To provide a highly accurate temperature sensor circuit. The temperature sensor circuit includes a first constant current circuit; a first diode in which a first voltage reflecting the temperature of an object to be detected is generated between an anode and a cathode in accordance with a first current supplied from the first constant current circuit; a second constant current circuit; a second diode which includes an oxide semiconductor and in which a second voltage is generated between an anode and a cathode in accordance with a second current supplied from the second constant current circuit; and an amplifier circuit which amplifies a difference between the first voltage and the second voltage.

Abstract translation: 提供高精度的温度传感器电路。 温度传感器电路包括第一恒流电路; 第一二极管，其中根据从第一恒流电路提供的第一电流，在阳极和阴极之间产生反映待检测物体的温度的第一电压; 第二恒流电路; 第二二极管，其包括氧化物半导体，并且其中根据从第二恒流电路提供的第二电流在阳极和阴极之间产生第二电压; 以及放大器电路，其放大第一电压和第二电压之间的差。

公开(公告)号：US20130285470A1

公开(公告)日：2013-10-31

申请号：US13865407

申请日：2013-04-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Jun KOYAMA ,  Junichiro SAKATA

IPC: H03K17/56

CPC classification number: H03K17/56 ,  H02M7/217 ,  H02M2001/0006 ,  H03K17/063 ,  H03K19/0013 ,  Y10T307/74

Abstract: A power supply circuit includes a first switch, a voltage regulator circuit connected to the first switch, and a control circuit for controlling the first switch. The control circuit includes a second switch, a third switch, and a voltage generation circuit. For controlling the first switch, first voltage output from the voltage generation circuit is applied to the first switch through the second switch, and second voltage output from the voltage generation circuit is applied to the first switch through the third switch. Power consumption of the power supply circuit can be reduced.

Abstract translation: 电源电路包括第一开关，连接到第一开关的稳压器电路和用于控制第一开关的控制电路。 控制电路包括第二开关，第三开关和电压产生电路。 为了控制第一开关，通过第二开关将来自电压产生电路的第一电压输出施加到第一开关，并且从电压产生电路输出的第二电压通过第三开关施加到第一开关。 可以减少电源电路的功耗。

公开(公告)号：US20130241965A1

公开(公告)日：2013-09-19

申请号：US13780435

申请日：2013-02-28

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Jun KOYAMA

IPC: G09G3/34

CPC classification number: G09G3/3406 ,  G09G3/32 ,  G09G2300/0842 ,  G09G2300/0852 ,  G09G2300/0861

Abstract: Display defects of a display device are suppressed. The display device includes in each pixel, a light-emitting element, a driving transistor which supplies current to the light-emitting element, and transistors in each of which a channel is formed in an oxide semiconductor layer. A transistor which controls whether to electrically connect a gate and a source of the driving transistor provided in each pixel is provided. The above transistor and a transistor which controls electrical connection between the gate of the driving transistor and another node are transistors in each of which a channel is formed in an oxide semiconductor layer. Accordingly, charge stored in the node electrically connected to the gate of the driving transistor can be arbitrarily retained or released. Consequently, display defects of the display device can be suppressed.

Abstract translation: 抑制显示装置的显示缺陷。 显示装置在每个像素中包括发光元件，向发光元件供给电流的驱动晶体管，以及在氧化物半导体层中形成沟道的晶体管。 提供控制是否电连接设置在每个像素中的驱动晶体管的栅极和源极的晶体管。 上述晶体管和控制驱动晶体管的栅极与另一个节点之间的电连接的晶体管是在氧化物半导体层中形成沟道的晶体管。 因此，可以任意地保持或释放存储在电连接到驱动晶体管的栅极的节点中的电荷。 因此，可以抑制显示装置的显示缺陷。

公开(公告)号：US20130200367A1

公开(公告)日：2013-08-08

申请号：US13751767

申请日：2013-01-28

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Satoru SAITO ,  Terumasa IKEYAMA

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/41733

Abstract: An object of one embodiment of the present invention is to provide a highly reliable semiconductor device by giving stable electric characteristics to a transistor including an oxide semiconductor film. The semiconductor device includes a gate electrode layer over a substrate, a gate insulating film over the gate electrode layer, an oxide semiconductor film over the gate insulating film, a drain electrode layer provided over the oxide semiconductor film to overlap with the gate electrode layer, and a source electrode layer provided to cover an outer edge portion of the oxide semiconductor film. The outer edge portion of the drain electrode layer is positioned on the inner side than the outer edge portion of the gate electrode layer.

公开(公告)号：US20130200366A1

公开(公告)日：2013-08-08

申请号：US13751753

申请日：2013-01-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Hiroyuki MIYAKE ,  Kouhei TOYOTAKA

IPC: H01L29/786

CPC classification number: H01L29/78693 ,  H01L29/41733 ,  H01L29/7869

Abstract: To provide a highly reliable semiconductor device in which a transistor including an oxide semiconductor film has stable electric characteristics. The semiconductor device includes a gate electrode layer over a substrate, a gate insulating film over the gate electrode layer, an oxide semiconductor film over the gate insulating film, a drain electrode layer which is over the oxide semiconductor film so as to overlap with the gate electrode layer, and a source electrode layer provided so as to cover part of an outer edge portion of the oxide semiconductor film. An outer edge portion of the drain electrode layer is on an inner side than an outer edge portion of the gate electrode layer.

Abstract translation: 为了提供一种高可靠性的半导体器件，其中包括氧化物半导体膜的晶体管具有稳定的电特性。 半导体器件包括在基板上的栅极电极层，栅极电极层上的栅极绝缘膜，栅极绝缘膜上的氧化物半导体膜，位于氧化物半导体膜上方以与栅极重叠的漏极层 电极层和设置为覆盖氧化物半导体膜的外缘部的一部分的源电极层。 漏电极层的外缘部位于比栅电极层的外缘部更内侧。

公开(公告)号：US20130099299A1

公开(公告)日：2013-04-25

申请号：US13672973

申请日：2012-11-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  G11C5/063 ,  G11C11/403 ,  G11C11/405 ,  G11C16/02 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L28/60

Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of times of writing operations. A semiconductor device includes a source-bit line, a first signal line, a second signal line, a word line, and a memory cell connected between the source-bit lines. The memory cell includes a first transistor, a second transistor, and a capacitor. The second transistor is formed including an oxide semiconductor material. A gate electrode of the first transistor, one of a source and drain electrodes, and one of electrodes of the capacitor are electrically connected to one another. The source-bit line and a source electrode of the first transistor are electrically connected to each other. Another source-bit line adjacent to the above source-bit line and a drain electrode of the first transistor are electrically connected to each other.

Abstract translation: 目的是提供一种具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保留存储的数据，并且对写入操作的次数没有限制。 半导体器件包括源极线，第一信号线，第二信号线，字线和连接在源极线之间的存储单元。 存储单元包括第一晶体管，第二晶体管和电容器。 形成包括氧化物半导体材料的第二晶体管。 第一晶体管的栅极，源极和漏极之一以及电容器的电极中的一个彼此电连接。 第一晶体管的源极线和源电极彼此电连接。 与上述源极线相邻的另一个源极线和第一晶体管的漏极彼此电连接。

公开(公告)号：US20250159939A1

公开(公告)日：2025-05-15

申请号：US19020084

申请日：2025-01-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Junichiro SAKATA ,  Jun KOYAMA

IPC: H10D30/67 ,  H01L21/02 ,  H10D62/80 ,  H10D86/40 ,  H10D86/60 ,  H10D99/00

Abstract: A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit.

公开(公告)号：US20250142973A1

公开(公告)日：2025-05-01

申请号：US19010328

申请日：2025-01-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kouhei TOYOTAKA ,  Jun KOYAMA ,  Hiroyuki MIYAKE

IPC: H10D86/60 ,  G02F1/1334 ,  G02F1/1337 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/20 ,  G09G3/3233 ,  G09G3/3258 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/36 ,  G11C19/28 ,  H10D30/67 ,  H10D86/40

Abstract: A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.