公开(公告)号：US20070026668A1

公开(公告)日：2007-02-01

申请号：US11457888

申请日：2006-07-17

申请人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

发明人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

IPC分类号： H01L21/465

CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76807

摘要： A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.

摘要翻译： 公开了一种通过蚀刻底部蚀刻停止层去除铜镶嵌结构中的氮化硅或氮化物基底部蚀刻停止层的方法，该方法使用含有氟和氧的高密度，高自由基浓度等离子体来最小化背面 底层蚀刻停止层下面的铜的溅射以及由等离子体引起的低k层间电介质的表面粗糙化。

公开(公告)号：US20060205224A1

公开(公告)日：2006-09-14

申请号：US11318934

申请日：2005-12-27

申请人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

发明人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/32139 ,  H01L21/28123

摘要： Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.

公开(公告)号：US20060086690A1

公开(公告)日：2006-04-27

申请号：US10971265

申请日：2004-10-21

申请人： Ming-Huan Tsai ,  Fong-Yuh Yen ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Fong-Yuh Yen ,  Hun-Jan Tao

IPC分类号： C23F1/00 ,  C03C25/68 ,  B44C1/22

CPC分类号： H01L21/31116

摘要： A method of dry etching a dielectric layer is provided that prevents or significantly reduces deep ultraviolet photoresist damage and bird's beak problems. The dry etch method provided comprises the steps of providing a substrate having a dielectric layer overlying at least a portion of the substrate's surface; applying a deep ultraviolet (DUV) photoresist mask having a pattern of exposed area on at least a portion of the dielectric layer; and etching the masked dielectric layer with a plasma formed from a mixture of gases comprising a gaseous fluorine species, hydrogen, and helium.

摘要翻译： 提供了干蚀刻电介质层的方法，其防止或显着降低深紫外光致抗蚀剂损伤和鸟嘴问题。 所提供的干蚀刻方法包括以下步骤：提供具有覆盖在基底表面的至少一部分上的介电层的基底; 在所述电介质层的至少一部分上施加具有暴露区域图案的深紫外（DUV）光致抗蚀剂掩模; 并用由包含气态氟物质，氢气和氦气的气体混合物形成的等离子体蚀刻掩蔽的电介质层。

公开(公告)号：US06974730B2

公开(公告)日：2005-12-13

申请号：US10739476

申请日：2003-12-17

申请人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

发明人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78621 ,  H01L29/78654

摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.

摘要翻译： 用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。 该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。 根据上述特征，以增强的性能制造场效应晶体管器件。

公开(公告)号：US20050133827A1

公开(公告)日：2005-06-23

申请号：US10738239

申请日：2003-12-17

申请人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

发明人： Ming-Jie Huang ,  Shu-Chih Yang ,  Huan-Just Lin ,  Yung-Tin Chen ,  Hun-Jan Tao

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L29/745

CPC分类号： H01L21/32139 ,  H01L21/28123

摘要： Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.

摘要翻译： 公开了用于形成用于半导体器件的超窄栅极的大规模修整。 蚀刻在半导体晶片上的图案化软掩模层下方的半导体晶片上的硬掩模层，以使硬掩模层的宽度变窄。 修剪硬掩模层以进一步缩小已经去除软掩模层的硬掩模层的宽度。 蚀刻半导体晶片上的硬掩模层下方的至少栅极电极层，导致栅极电极层的宽度与被修整的硬掩模层的宽度基本相同。 蚀刻的栅极电极层形成半导体晶片上的超窄栅电极，其中硬掩模层被去除。

公开(公告)号：US20050095869A1

公开(公告)日：2005-05-05

申请号：US10701825

申请日：2003-11-05

申请人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

发明人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76807

摘要： A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.

摘要翻译： 通过使用包含氟和氧的高密度，高自由基浓度的等离子体蚀刻底部蚀刻停止层来去除铜镶嵌结构中的氮化硅或氮化物基底部蚀刻停止层的方法，以最小化底部的铜的反溅射 蚀刻停止层和由等离子体引起的低k层间电介质的表面粗糙化。

公开(公告)号：US06780782B1

公开(公告)日：2004-08-24

申请号：US10357579

申请日：2003-02-04

申请人： Ming-Huan Tsai ,  Hun-Jan Tao ,  Tsang Jiuh Wu ,  Ju Wang Hsu

发明人： Ming-Huan Tsai ,  Hun-Jan Tao ,  Tsang Jiuh Wu ,  Ju Wang Hsu

IPC分类号： H01L21302

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144

摘要： An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique combination of gaseous components in a plasma etching process which is used to dry develop the bi-level resist mask as well as etch through a silicon oxide dielectric layer. The gaseous components comprise a mixture of a fluorine containing gas, such as C4F8, C5F8, C4F6, CHF3 or similar species, an inert gas, such as helium or argon, an optional weak oxidant, such as CO or O2 or similar species, and a nitrogen source, such as N2, N2O, or NH3 or similar species. The patterned masking layer can be used to reliably etch contact holes in silicon oxide layers on semiconductor substrates, where the holes have diameters of about 0.1 micron or less.

摘要翻译： 已经开发了一种通过介电层蚀刻非常小的接触孔的改进方法，其用于在半导体衬底上形成的多层集成电路中分离导电层。 该方法在抗蚀剂结构中使用双层ARC涂层，并且在等离子体蚀刻工艺中使用气态组分的独特组合，其用于干燥显影双电平抗蚀剂掩模以及通过氧化硅介电层进行蚀刻。 气态组分包括含氟气体如C 4 F 8，C 5 F 8，C 4 F 6，CHF 3或类似物质，惰性气体如氦气或氩气，任选的弱氧化剂如CO或O 2或类似物质的混合物，以及 氮源，例如N 2，N 2 O或NH 3或类似物质。 图案化掩模层可用于可靠地蚀刻半导体衬底上的氧化硅层中的接触孔，其中孔的直径为约0.1微米或更小。

公开(公告)号：US06326296B1

公开(公告)日：2001-12-04

申请号：US09108867

申请日：1998-07-01

申请人： Chia Shiung Tsai ,  Hun-Jan Tao

发明人： Chia Shiung Tsai ,  Hun-Jan Tao

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3185 ,  H01L2221/1036

摘要： A new method of forming a dual damascene interconnect is disclosed for manufacturing semiconductor substrates. A contact/via hole is first formed in a first dielectric layer formed over a substructure of a substrate having devices formed therein and/or metal layers formed thereon. The contact/via hole is filled with a protective material prior to forming a second dielectric layer. Conductive line opening is formed in the second dielectric layer and over the contact/via hole having the protective material in it. The protective material protects the edge of the contact/via hole from damage due to the second etching of the conductive line opening. Thus, a dual damascene structure is disclosed wherein the integrity of the edge of the contact/via hole is preserved, avoiding any reliability problems in the semiconductor product.

摘要翻译： 公开了一种形成双镶嵌互连的新方法，用于制造半导体衬底。 接触/通孔首先形成在形成在其上形成有器件和/或其上形成金属层的衬底的子结构之上的第一电介质层中。 在形成第二电介质层之前，接触/通孔填充有保护材料。 导电线路开口形成在第二电介质层中并且在其中具有保护材料的接触/通孔之上。 保护材料保护接触/通孔的边缘免受由于导电线开口的第二次蚀刻的损害。 因此，公开了一种双镶嵌结构，其中保留了接触/通孔的边缘的完整性，避免了半导体产品中的任何可靠性问题。

公开(公告)号：US6040248A

公开(公告)日：2000-03-21

申请号：US104032

申请日：1998-06-24

申请人： Chao-Cheng Chen ,  Ming-Hsin Huang ,  Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Chao-Cheng Chen ,  Ming-Hsin Huang ,  Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/302 ,  C23F1/02 ,  H01L21/461

CPC分类号： H01L21/31138 ,  H01L21/76802

摘要： A process for plasma etching of contact and via openings in low-k organic polymer dielectric layers is described which overcomes problems of sidewall bowing and hardmask pattern deterioration by etching the organic layer in a high density plasma etcher with a chlorine/inert gas plasma. By adding chlorine to the oxygen/inert gas plasma, the development of an angular aspect or faceting of the hardmask pattern edges by ion bombardment is abated. Essentially vertical sidewalls are obtained in the openings etched in the organic polymer layer while hardmask pattern integrity is maintained. The addition of a passivating agent such as nitrogen, BCl.sub.3, or CHF.sub.3 to the etchant gas mixture further improves the sidewall profile by reducing bowing through protective polymer formation.

摘要翻译： 描述了一种用于等离子体蚀刻低k有机聚合物介电层中的接触和通孔开口的方法，其通过用氯/惰性气体等离子体在高密度等离子体蚀刻机中蚀刻有机层来克服侧壁弯曲和硬掩模图案劣化的问题。 通过向氧/惰性气体等离子体中加入氯，减少了通过离子轰击形成硬掩模图案边缘的角度方面或刻面。 在保持硬掩模图案完整性的同时，在有机聚合物层中蚀刻的开口中获得基本垂直的侧壁。 钝化剂如氮气，BCl3或CHF3添加到蚀刻剂气体混合物中，通过减少通过保护性聚合物形成的弯曲来进一步改善侧壁轮廓。

公开(公告)号：US5694207A

公开(公告)日：1997-12-02

申请号：US762076

申请日：1996-12-09

申请人： Shu Chi Hung ,  Hun-Jan Tao

发明人： Shu Chi Hung ,  Hun-Jan Tao

IPC分类号： G01N21/73 ,  H01L21/3065 ,  G01N21/62

CPC分类号： H01L21/3065 ,  G01N21/73

摘要： The etch rate in a plasma etching system has been monitored in-situ by using optical emission spectroscopy to measure the intensities of two or more peaks in the radiation spectrum and then using the ratio of two such peaks as a direct measure of etch rate. Examples of such peaks occur at 338.5 and 443.7 nm and at 440.6 and 437.6 nm for the fluoride/SOG system. Alternately, the intensities of at least four such peaks may be measured and the product of two ratios may be used. Examples of peaks used in this manner occurred at 440.5, 497.2 and 502.3 nm, also for the fluoride/SOG system. The method is believed to be general and not limited to fluoride/SOG.

摘要翻译： 已经通过使用光发射光谱法原位监测等离子体蚀刻系统中的蚀刻速率，以测量辐射光谱中两个或更多个峰的强度，然后使用两个这样的峰的比例作为蚀刻速率的直接测量。 对于氟化物/ SOG体系，这些峰的实例在338.5和443.7nm以及440.6和437.6nm处发生。 或者，可以测量至少四个这样的峰的强度，并且可以使用两个比率的乘积。 以这种方式使用的峰的实例发生在440.5,497.2和502.3nm，也用于氟化物/ SOG体系。 该方法被认为是通用的，不限于氟化物/ SOG。