公开(公告)号：US20070046333A1

公开(公告)日：2007-03-01

申请号：US11507622

申请日：2006-08-22

申请人： Masatomo Eimitsu ,  Yasushi Aoki

发明人： Masatomo Eimitsu ,  Yasushi Aoki

IPC分类号： H03K19/094

CPC分类号： H03K3/35613

摘要： A differential output circuit includes a bias circuit connected with a first voltage. An input circuit section includes first and second MOS transistors of a first conductive type, and the first and second MOS transistors are connected with the first voltage through the bias circuit, and gates of the first and second MOS transistors receive a differential input signal. Third and fourth MOS transistors of a second conductive type are connected with the first and second MOS transistors through first and second resistance elements, respectively, and connected with a second voltage. A first connection node between the first MOS transistor and the first resistance element is connected with a gate of the fourth MOS transistor, and a second connection node between the second MOS transistor and the second resistance element is connected with a gate of the third MOS transistor. A differential output signal is outputted from a first output node between the first resistance element and the third MOS transistor and a second output node between the second resistance element and the fourth MOS transistor in response to the differential input signal.

摘要翻译： 差分输出电路包括与第一电压连接的偏置电路。 输入电路部分包括第一导电类型的第一和第二MOS晶体管，第一和第二MOS晶体管通过偏置电路与第一电压连接，第一和第二MOS晶体管的栅极接收差分输入信号。 第二导电类型的第三和第四MOS晶体管分别通过第一和第二电阻元件与第一和第二MOS晶体管连接，并与第二电压连接。 第一MOS晶体管和第一电阻元件之间的第一连接节点与第四MOS晶体管的栅极连接，第二MOS晶体管和第二电阻元件之间的第二连接节点与第三MOS晶体管的栅极连接 。 响应于差分输入信号，差分输出信号从第一电阻元件和第三MOS晶体管之间的第一输出节点和第二电阻元件与第四MOS晶体管之间的第二输出节点输出。

公开(公告)号：US20070045770A1

公开(公告)日：2007-03-01

申请号：US11510648

申请日：2006-08-28

申请人： Yasushi Aoki

发明人： Yasushi Aoki

IPC分类号： H01L29/00

CPC分类号： H01L29/41758 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/78

摘要： A semiconductor device is composed of: an array of CMOS primitive cells provided in a circuit region; a power supply line extended along the array of the CMOS primitive cells and connected to the CMOS primitive cells; a ground line extended along the array of the CMOS primitive cells and connected to the CMOS primitive cells; a first decoupling capacitor provided under the power supply line; a second decoupling capacitor provided under the ground line. The first decoupling capacitor is formed of a PMOS transistor having a gate connected to the ground line. At least one of the source and drain of the PMOS transistor is connected to the power supply line. The second decoupling capacitor is formed of an NMOS transistor having a gate connected to the power supply line. At least one of the source and drain of the NMOS transistor is connected to the ground line.

摘要翻译： 半导体器件由以下部件组成：设置在电路区域中的CMOS原电池阵列; 电源线沿着CMOS原始单元的阵列延伸并连接到CMOS原始单元; 沿着CMOS原始单元的阵列延伸并连接到CMOS原始单元的接地线; 在电源线下设置的第一去耦电容器; 位于地线下方的第二去耦电容器。 第一去耦电容器由具有连接到地线的栅极的PMOS晶体管形成。 PMOS晶体管的源极和漏极中的至少一个连接到电源线。 第二去耦电容器由具有与电源线连接的栅极的NMOS晶体管形成。 NMOS晶体管的源极和漏极中的至少一个连接到接地线。

公开(公告)号：US07104058B2

公开(公告)日：2006-09-12

申请号：US11002893

申请日：2004-12-03

申请人： Isao Matsuno ,  Kazuhiro Tagata ,  Yasushi Aoki ,  Kenji Suzuki

发明人： Isao Matsuno ,  Kazuhiro Tagata ,  Yasushi Aoki ,  Kenji Suzuki

IPC分类号： B60T13/14 ,  B60T13/12 ,  B60T11/20

CPC分类号： B60T13/147 ,  B60T11/16 ,  B60T13/145

摘要： In a vehicle braking system, a backup piston pushes a master piston directly from behind when hydraulic pressure of a boosted hydraulic pressure chamber decreases. The backup piston has a piston body which is slidably fitted in a casing, and a pusher which is slidably fitted in the casing with a seal diameter smaller than seal diameters of the master piston and the piston body and which extends to the front end of the piston body, to push the master piston from behind. An annular input chamber communicated with a hydraulic power source is formed between the backup piston and the casing. When the pusher pushes the master piston forward, amount of volume increased in the boosted hydraulic pressure chamber is set to be substantially equal to amount of volume decreased in the input chamber. Thus, it is possible to avoid increase in the hydraulic pressure of the boosted hydraulic pressure chamber during forward movement of the backup piston, using a simple configuration with a reduced number of parts.

摘要翻译： 在车辆制动系统中，当升压液压室的液压下降时，备用活塞直接从后方推动主活塞。 支撑活塞具有可滑动地装配在壳体中的活塞体和可滑动地装配在壳体中的推动器，其具有小于主活塞和活塞体的密封直径的密封直径，并且延伸到 活塞体，从后面推动主活塞。 在支撑活塞和壳体之间形成有与液压动力源连通的环形输入室。 当推动器向前推动主活塞时，增压液压室中的体积增加量被设定为基本上等于在输入室中减小的体积量。 因此，通过使用减少部件数量的简单构造，可以避免在后备活塞向前运动期间增压液压室的液压升高。

公开(公告)号：US07077482B2

公开(公告)日：2006-07-18

申请号：US11002652

申请日：2004-12-03

申请人： Isao Matsuno ,  Kazuhiro Tagata ,  Yasushi Aoki ,  Kenji Suzuki

发明人： Isao Matsuno ,  Kazuhiro Tagata ,  Yasushi Aoki ,  Kenji Suzuki

IPC分类号： B60T8/44

CPC分类号： B60T13/142 ,  B60T8/4077 ,  B60T11/16 ,  B60T13/145 ,  B60T13/147

摘要： A simulator piston is slidably fitted in a control piston to form a stroke liquid chamber between itself and an end wall of a control piston. A port which is closed at a forward limit of the control piston with respect to a backup piston is provided in the end wall of the control piston. A first reaction piston which constantly abuts against the end wall of the control piston and a second reaction piston which abuts against the end wall of the control piston when the control piston advances toward the backup piston through a predetermined travel distance or more, are relatively slidably mounted on the backup piston so that hydraulic pressure of the boosted hydraulic pressure chamber acts on their front ends. Thus, it is possible to curb increase in a stroke and reaction of a brake operating member which would be invalidated by a brake stroke simulator when a hydraulic power source fails, and avoid insufficient strokes of the brake operating member even if spikes are inputted.

摘要翻译： 模拟器活塞可滑动地装配在控制活塞中，以在其自身与控制活塞的端壁之间形成行程液体室。 在控制活塞的端壁中设置有在控制活塞相对于后备活塞的向前极限处封闭的端口。 当控制活塞朝着备用活塞前进预定的行进距离或更长时，与第一反作用活塞紧密接触的控制活塞的端壁和第二反作用活塞抵靠控制活塞的端壁， 安装在备用活塞上，使得升压液压室的液压作用在其前端。 因此，当液压电源发生故障时，可以抑制由制动行程模拟器无效的制动操作构件的行程和反应的增加，并且即使在输入尖峰时也避免制动操作构件的冲程不足。

公开(公告)号：US20050160730A1

公开(公告)日：2005-07-28

申请号：US11002893

申请日：2004-12-03

申请人： Isao Matsuno ,  Kazuhiro Tagata ,  Yasushi Aoki ,  Kenji Suzuki

发明人： Isao Matsuno ,  Kazuhiro Tagata ,  Yasushi Aoki ,  Kenji Suzuki

IPC分类号： B60T11/20 ,  B60T11/16 ,  B60T13/12 ,  B60T13/14 ,  B60T13/00

CPC分类号： B60T13/147 ,  B60T11/16 ,  B60T13/145

摘要： In a vehicle braking system, a backup piston pushes a master piston directly from behind when hydraulic pressure of a boosted hydraulic pressure chamber decreases. The backup piston has a piston body which is slidably fitted in a casing, and a pusher which is slidably fitted in the casing with a seal diameter smaller than seal diameters of the master piston and the piston body and which extends to the front end of the piston body, to push the master piston from behind. An annular input chamber communicated with a hydraulic power source is formed between the backup piston and the casing. When the pusher pushes the master piston forward, amount of volume increased in the boosted hydraulic pressure chamber is set to be substantially equal to amount of volume decreased in the input chamber. Thus, it is possible to avoid increase in the hydraulic pressure of the boosted hydraulic pressure chamber during forward movement of the backup piston, using a simple configuration with a reduced number of parts.

摘要翻译： 在车辆制动系统中，当升压液压室的液压下降时，备用活塞直接从后方推动主活塞。 支撑活塞具有可滑动地装配在壳体中的活塞体和可滑动地装配在壳体中的推动器，其具有小于主活塞和活塞体的密封直径的密封直径，并且延伸到 活塞体，从后面推动主活塞。 在支撑活塞和壳体之间形成有与液压动力源连通的环形输入室。 当推动器向前推动主活塞时，增压液压室中的体积增加量被设定为基本上等于在输入室中减小的体积量。 因此，通过使用减少部件数量的简单构造，可以避免在后备活塞向前运动期间增压液压室的液压升高。

公开(公告)号：US06278755B1

公开(公告)日：2001-08-21

申请号：US09567072

申请日：2000-05-08

申请人： Mitsuo Baba ,  Yasushi Aoki ,  Minoru Kayano ,  Yuuji Takahashi ,  Atsushi Katayama

发明人： Mitsuo Baba ,  Yasushi Aoki ,  Minoru Kayano ,  Yuuji Takahashi ,  Atsushi Katayama

IPC分类号： H04L700

CPC分类号： H04L7/0338

摘要： A bit synchronization circuit extracts the central phase of an eye opening irrespective of a jitter distribution of input data to maintain an optimum timing adjustment margin. The bit synchronization circuit has a data edge detector for comparing the phases of an edge of the input data and m-phase clock signals divided from a reference clock. Data edge phase information from the data edge detector is accumulated by a phase accumulation register, which stores the jitter distribution of the input data as accumulated phase information. Based on the accumulated phase information, an eye center phase calculator decodes the negative and positive ends of a jitter range as negative jitter range information and positive jitter range information, and calculates a phase control direction in relation to an extracted phase value which represents a presently selected clock phase. A correction circuit extracts the positional relationship between a present eye opening width and the extracted phase value, and clears the accumulated phase information to increase the eye opening width.

摘要翻译： 位同步电路提取眼睛开放的中心相位，而与输入数据的抖动分布无关，以保持最佳定时调整余量。 比特同步电路具有数据边缘检测器，用于比较输入数据的边沿和从参考时钟划分的m相时钟信号的相位。 来自数据边缘检测器的数据边沿相位信息由相位累加寄存器累加，该相位累加寄存器将输入数据的抖动分布存储为累积相位信息。 基于积累的相位信息，眼中心相位计算器将抖动范围的负端和正端解码为负抖动范围信息和正抖动范围信息，并且计算与提取的相位值相关的相位控制方向，该相位控制方向表示当前 选择时钟相位。 校正电路提取当前眼睛开口宽度与提取的相位值之间的位置关系，并且清除累积的相位信息以增加眼睛开口宽度。

公开(公告)号：US6002731A

公开(公告)日：1999-12-14

申请号：US995345

申请日：1997-12-22

申请人： Yasushi Aoki ,  Mitsuo Baba

发明人： Yasushi Aoki ,  Mitsuo Baba

IPC分类号： H04L25/40 ,  H03L7/081 ,  H03L7/085 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033

CPC分类号： H04L7/0338 ,  H03L7/0814 ,  H03L7/085

摘要： In a data synchronization circuit for obtaining a clock synchronized with bits of received data to submit the received data to retiming, it is achieved that a phase synchronization without use of a feedback loop configuration giving rise to oscillations is performed. The received data are devided according to the frequency in a frequency dividing circuit. This frequency divided output and the respective n-phase clocks are compared in phase to generate a specific signal to specify one of n-phase clocks having predetermined phase relations to the frequency divided output. While, on the other hand, the change points of the frequency divided output are synchronized with the extracted clock of a clock selector to average the specific signal with the timing of this change point synchronization signal. One of n-phase clocks is extracted in conformity with the state of this averaged output to make an extracted clock and to subject the received data to retiming in a flip-flop by using this clock.

摘要翻译： 在用于获得与接收数据的位同步的时钟的数据同步电路中，提交接收的数据以重定时，实现了不使用引起振荡的反馈回路配置的相位同步。 接收的数据根据​​分频电路中的频率分配。 该分频输出和相应的n相时钟相位进行比较，以产生特定信号，以指定与分频输出具有预定相位关系的n相时钟。 而另一方面，分频输出的变化点与提取的时钟选择器的时钟同步，以与该变化点同步信号的定时平均特定信号。 根据该平均输出的状态提取n相时钟中的一个，以提取时钟并且通过使用该时钟使接收到的数据在触发器中重新定时。

公开(公告)号：US5572557A

公开(公告)日：1996-11-05

申请号：US253062

申请日：1994-06-02

申请人： Yasushi Aoki

发明人： Yasushi Aoki

IPC分类号： H03L7/00 ,  G06F1/10 ,  G06F1/12 ,  H03L7/07 ,  H03L7/081 ,  H04L7/00 ,  H03D3/24

CPC分类号： H03L7/0812 ,  G06F1/10 ,  H03L7/07 ,  H04L7/0008 ,  H04L7/0037

摘要： A semiconductor integrated circuit device including input and output registers, a data-processing circuit block disposed between the registers, a first PLL circuit for supplying a first output clock signal to the input register in response to an input clock signal, and a second PLL circuit for supplying a second output clock signal to the output register in response to the input clock signal. The input register transfers a data signal stored therein to the output register in response to the first output clock signal. The output register stores the data signal and transfers it to another device in response to the second output clock signal. The first and second PLL circuits supply the first and second output clock signals to the input and output registers with keeping the phase differences constant, respectively. The data signal stored in the input register can be correctly transferred to the output register, and the data signal stored in the output register can be correctly transferred to an input register of another semiconductor integrated circuit device even if the clock skew arises.

摘要翻译： 一种半导体集成电路装置，包括输入和输出寄存器，设置在寄存器之间的数据处理电路块，用于响应于输入时钟信号向输入寄存器提供第一输出时钟信号的第一PLL电路和第二PLL电路 用于响应于输入时钟信号向输出寄存器提供第二输出时钟信号。 输入寄存器响应于第一输出时钟信号将存储在其中的数据信号传送到输出寄存器。 输出寄存器存储数据信号，并响应于第二个输出时钟信号将其传送到另一个设备。 第一和第二PLL电路将第一和第二输出时钟信号分别提供给输入和输出寄存器，同时保持相位差恒定。 存储在输入寄存器中的数据信号可以正确地传送到输出寄存器，并且即使产生时钟偏差，存储在输出寄存器中的数据信号也可以被正确地传送到另一个半导体集成电路器件的输入寄存器。

公开(公告)号：US5528198A

公开(公告)日：1996-06-18

申请号：US458074

申请日：1995-06-01

申请人： Mitsuo Baba ,  Yasushi Aoki

发明人： Mitsuo Baba ,  Yasushi Aoki

IPC分类号： H03L7/087 ,  H03L7/085 ,  H04L7/033 ,  H03L7/099

CPC分类号： H03L7/085 ,  H04L7/033 ,  H04L7/0337 ,  H03L7/087

摘要： A plurality of clock signals at an identical frequency but with different phases are oscillated by a voltage-controlled oscillator beforehand, and selection is made of one of the clock signals whose phase is closest to that of the data signal each time the data signal rises. In parallel with the selection of phase, a phase/frequency comparison is made between any one of the clock signals output from the voltage-controlled oscillator and the selected clock signal. After the comparison, the oscillation frequency of the voltage-controlled oscillator is converted for their matching. This matching allows acquisition of a clock signal with the closest phase immediately after arrival of the data signal, and acquisition of an extraction clock signal with the frequency and phase matched in a short time by parallel conversion of the oscillation frequency of the voltage-controlled oscillator.

摘要翻译： 以相同的频率但是具有不同相位的多个时钟信号预先由压控振荡器振荡，并且每次数据信号上升时，选择其相位最接近数据信号的时钟信号之一。 与相位的选择并行，在从压控振荡器输出的任何一个时钟信号和所选择的时钟信号之间进行相位/频率比较。 比较后，将压控振荡器的振荡频率进行匹配。 该匹配允许采集紧随数据信号到达之后最接近的相位的时钟信号，并且通过并联转换压控振荡器的振荡频率来获取频率和相位在短时间内匹配的提取时钟信号 。

公开(公告)号：US5493536A

公开(公告)日：1996-02-20

申请号：US289255

申请日：1994-08-11

申请人： Yasushi Aoki

发明人： Yasushi Aoki

IPC分类号： G11C11/41 ,  G11C11/412 ,  G11C8/00

CPC分类号： G11C11/41 ,  G11C11/412

摘要： A semiconductor memory circuit contains an array of memory cells, each of which contains a data latch formed of cross-coupled two inverters. First and second gate elements connected in series are placed between an output end of the latch and a reference point. Third and fourth gate elements connected in series are placed between the other output end and the reference point. Fifth, sixth and seventh gate elements connected in series are placed between the reference point and a read data line. During a write operation, while keeping the first and fourth gate elements and one of the second and third gate elements closed, a data to be stored is written in the latch through one of the pair of write data lines. During a read operation, while keeping the sixth and seventh gate elements closed, a stored data in the latch is read out through the read data line. Read and write operations can be performed without affecting the unselected memory cells, which reduces power dissipation during write and read operations.

摘要翻译： 半导体存储器电路包含存储器单元的阵列，每个存储单元包含由交叉耦合的两个反相器形成的数据锁存器。 串联连接的第一和第二栅极元件被放置在闩锁的输出端和参考点之间。 串联连接的第三和第四栅极元件位于另一个输出端和参考点之间。 将串联连接的第五，第六和第七栅极元件放置在参考点和读取数据线之间。 在写入操作期间，在保持第一和第四栅极元件以及第二和第三栅极元件之一关闭的同时，通过一对写入数据线之一将要存储的数据写入锁存器。 在读取操作期间，在保持第六和第七门元件关闭的同时，通过读取数据线读出锁存器中存储的数据。 可以在不影响未选择的存储单元的情况下执行读写操作，从而降低写操作和读操作期间的功耗。