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51.发明申请公开(公告)号：US20110068837A1
公开(公告)日：2011-03-24
申请号：US12565624
申请日：2009-09-23
CPC分类号： H03K3/00 , H03K19/0002 , H03K19/09425
摘要： An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.
摘要翻译： 集成电路装置包括适于从内部或外部驱动器接收信号的焊盘以及包括耦合到焊盘的输入端的输入缓冲电路。 输入缓冲器电路包括具有控制端子的传输晶体管，连接到焊盘的第一导电端子和连接到第一电压的第二导电端子。 输入缓冲电路还包括具有电耦合到传输晶体管的控制端的端子的锁存器。 所述输入缓冲器电路还包括耦合到所述锁存器的电路，所述电路包括反馈晶体管，所述反馈晶体管具有电耦合到所述焊盘的控制端子，电耦合到第二电压的第一导电端子以及耦合到所述锁存器的第二导电端子。
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公开(公告)号：US07889572B2
公开(公告)日：2011-02-15
申请号：US12204009
申请日：2008-09-04
IPC分类号： G11C7/00
摘要： A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory cell. The reading control circuit is for selectively applying a working voltage to the source line.
摘要翻译： 存储器包括多个存储区域，每个存储器区域包括目标存储器单元，源极线，位线和读取控制电路。 源极线耦合到目标存储器单元的第一端子。 位线耦合到目标存储器单元的第二端子。 读取控制电路用于选择性地向源极线施加工作电压。
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公开(公告)号：US07885120B2
公开(公告)日：2011-02-08
申请号：US12465263
申请日：2009-05-13
申请人： Chun-Hsiung Hung , Wen-Chiao Ho , Kuen-Long Chang
发明人： Chun-Hsiung Hung , Wen-Chiao Ho , Kuen-Long Chang
IPC分类号： G11C16/06
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/0491 , G11C16/3454 , G11C2211/5621
摘要： A method for double programming of multi-level-cell (MLC) programming in a multi-bit-cell (MBC) of a charge trapping memory that includes a plurality of charge trapping memory cells is provided. The double programming method is conducted in two phrases, a pre-program phase and a post-program phase, and applied to a word line (a segment in a word line, a page in a word line, a program unit or a memory unit) of the charge trapping memory. A program unit can be defined by input data in a wide variety of ranges. For example, a program unit can be defined as a portion (such as a page, a group, or a segment) in one word line in which each group is selected for pre-program and pre-program-verify, either sequentially or in parallel with other groups in the same word line.
摘要翻译： 提供了一种用于在包括多个电荷捕获存储器单元的电荷俘获存储器的多位单元（MBC）中的多电平单元（MLC）编程的双重编程的方法。 双重编程方法在两个短语中进行，即预编程阶段和后期编程阶段，并且应用于字线（字线中的段，字线中的页，程序单元或存储单元 ）电荷捕获存储器。 程序单元可以由各种范围内的输入数据定义。 例如，程序单元可以被定义为一个字线中的每个组被选择用于预编程和预编程验证的部分（例如页面，组或段），顺序地或在 与同一字线上的其他组并行。
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公开(公告)号：US20110016288A1
公开(公告)日：2011-01-20
申请号：US12837823
申请日：2010-07-16
申请人： Kuen-Long Chang , Yufe-Feng Lin , Chun-Hsiung Hung
发明人： Kuen-Long Chang , Yufe-Feng Lin , Chun-Hsiung Hung
IPC分类号： G06F12/06
CPC分类号： G11C7/10 , G06F9/30149 , G06F9/342 , G06F9/3875
摘要： A serial flash memory and an address transmission method thereof. The serial flash memory selectively addresses a first memory space according to a first address length or addresses a second memory space according to a second address length longer than the first address length. If the first memory space is addressed according to the first address length, a first memory address is completely received within an address time duration so that data corresponding to the first memory address is initially outputted from a starting clock. In the address transmission method, if the second memory space is addressed according to the second address length, a portion of a second memory address is received within the address time duration. The other portion of the second memory address is received within a waiting time duration so that data corresponding to the second memory address is initially outputted from the starting clock.
摘要翻译： 串行闪存及其地址发送方法。 串行闪速存储器根据第一地址长度选择性地寻址第一存储器空间，或者根据长于第一地址长度的第二地址长度寻址第二存储器空间。 如果根据第一地址长度寻址第一存储器空间，则在地址持续时间内完全接收到第一存储器地址，从而从起始时钟开始输出与第一存储器地址对应的数据。 在地址发送方法中，如果根据第二地址长度寻址第二存储器空间，则在地址持续时间内接收第二存储器地址的一部分。 第二存储器地址的另一部分在等待时间段内被接收，使得对应于第二存储器地址的数据最初从起始时钟输出。
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公开(公告)号：US07869276B2
公开(公告)日：2011-01-11
申请号：US11946893
申请日：2007-11-29
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： A memory includes many memory regions. The memory regions have multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The first bit line is coupled to a first column of the multi-level cells. The second bit line is coupled to a second column of the multi-level cells. The data buffer is coupled to the first bit line and the second bit line and for storing data to be programmed into the multi-level cells. The protecting unit is coupled to the first bit line, the second bit line and the data buffer and is for preventing a programming error from occurring.
摘要翻译： 存储器包括许多存储器区域。 存储区具有多个多级单元。 每个存储器区域包括第一位线，第二位线，数据缓冲器和保护单元。 第一位线耦合到多级单元的第一列。 第二位线耦合到多电平单元的第二列。 数据缓冲器耦合到第一位线和第二位线，并用于存储要编程到多电平单元中的数据。 保护单元耦合到第一位线，第二位线和数据缓冲器，并且用于防止发生编程错误。
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公开(公告)号：US07710802B2
公开(公告)日：2010-05-04
申请号：US11850061
申请日：2007-09-05
IPC分类号： G11C7/00
CPC分类号： G11C29/08
摘要： A method for testing a memory includes the following steps. First, data is read from the memory and stored to a first temporary memory. Meanwhile, expected data corresponding to the data from the memory is written into a second temporary memory from a tester. Thereafter, the data in the first temporary memory and the expected data in the second temporary memory are compared with each other to judge whether the memory has an enough operation window.
摘要翻译： 用于测试存储器的方法包括以下步骤。 首先，从存储器读取数据并存储到第一临时存储器。 同时，与来自存储器的数据对应的期望数据从测试器写入第二临时存储器。 此后，将第一临时存储器中的数据和第二临时存储器中的预期数据彼此进行比较，以判断存储器是否具有足够的操作窗口。
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公开(公告)号：US20090219759A1
公开(公告)日：2009-09-03
申请号：US12465263
申请日：2009-05-13
申请人： Chun-Hsiung Hung , Wen-Chiao Ho , Kuen-Long Chang
发明人： Chun-Hsiung Hung , Wen-Chiao Ho , Kuen-Long Chang
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/0491 , G11C16/3454 , G11C2211/5621
摘要： A method for double programming of multi-level-cell (MLC) programming in a multi-bit-cell (MBC) of a charge trapping memory that includes a plurality of charge trapping memory cells is provided. The double programming method is conducted in two phrases, a pre-program phase and a post-program phase, and applied to a word line (a segment in a word line, a page in a word line, a program unit or a memory unit) of the charge trapping memory. A program unit can be defined by input data in a wide variety of ranges. For example, a program unit can be defined as a portion (such as a page, a group, or a segment) in one word line in which each group is selected for pre-program and pre-program-verify, either sequentially or in parallel with other groups in the same word line.
摘要翻译： 提供了一种用于在包括多个电荷俘获存储器单元的电荷俘获存储器的多位单元（MBC）中的多电平单元（MLC）编程的双重编程的方法。 双重编程方法在两个短语中进行，即预编程阶段和后期编程阶段，并且应用于字线（字线中的段，字线中的页，程序单元或存储单元 ）电荷捕获存储器。 程序单元可以由各种范围内的输入数据定义。 例如，程序单元可以被定义为一个字线中的每个组被选择用于预编程和预编程验证的部分（例如页面，组或段），顺序地或在 与同一字线上的其他组并行。
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公开(公告)号：US20090201725A1
公开(公告)日：2009-08-13
申请号：US12028405
申请日：2008-02-08
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： A method for programming a plurality of multi-level memory cells described herein includes iteratively changing a bias voltage applied to a first memory cell to program the first memory cell to a first threshold state and detecting when the first cell reaches a predetermined threshold voltage. The bias voltage applied to the first memory cell upon reaching the predetermined threshold voltage is recorded. A second memory cell is programmed to a second threshold state by applying an initial bias voltage to the second memory cell which is function of the recorded bias voltage.
摘要翻译： 用于编程本文所述的多个多电平存储器单元的方法包括迭代地改变施加到第一存储器单元的偏置电压，以将第一存储器单元编程为第一阈值状态，以及检测第一单元何时达到预定阈值电压。 记录在达到预定阈值电压时施加到第一存储单元的偏置电压。 通过对作为记录的偏置电压的函数的第二存储器单元施加初始偏置电压将第二存储单元编程为第二阈值状态。
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公开(公告)号：US07548462B2
公开(公告)日：2009-06-16
申请号：US11771310
申请日：2007-06-29
申请人： Chun-Hsiung Hung , Wen-Chiao Ho , Kuen-Long Chang
发明人： Chun-Hsiung Hung , Wen-Chiao Ho , Kuen-Long Chang
IPC分类号： G11C16/06
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/0491 , G11C16/3454 , G11C2211/5621
摘要： A method for double programming of multi-level-cell (MLC) programming in a multi-bit-cell (MBC) of a charge trapping memory that includes a plurality of charge trapping memory cells is provided. The double programming method is conducted in two phrases, a pre-program phase and a post-program phase, and applied to a word line (a segment in a word line, a page in a word line, a program unit or a memory unit) of the charge trapping memory. A program unit can be defined by input data in a wide variety of ranges. For example, a program unit can be defined as a portion (such as a page, a group, or a segment) in one word line in which each group is selected for pre-program and pre-program-verify, either sequentially or in parallel with other groups in the same word line.
摘要翻译： 提供了一种用于在包括多个电荷俘获存储器单元的电荷俘获存储器的多位单元（MBC）中的多电平单元（MLC）编程的双重编程的方法。 双重编程方法在两个短语中进行，即预编程阶段和后期编程阶段，并且应用于字线（字线中的段，字线中的页，程序单元或存储单元 ）电荷捕获存储器。 程序单元可以由各种范围内的输入数据定义。 例如，程序单元可以被定义为一个字线中的每个组被选择用于预编程和预编程验证的部分（例如页面，组或段），顺序地或在 与同一字线上的其他组并行。
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公开(公告)号：US20090059698A1
公开(公告)日：2009-03-05
申请号：US11850061
申请日：2007-09-05
IPC分类号： G11C29/00
CPC分类号： G11C29/08
摘要： A method for testing a memory includes the following steps. First, data is read from the memory and stored to a first temporary memory. Meanwhile, expected data corresponding to the data from the memory is written into a second temporary memory from a tester. Thereafter, the data in the first temporary memory and the expected data in the second temporary memory are compared with each other to judge whether the memory has an enough operation window.
摘要翻译： 用于测试存储器的方法包括以下步骤。 首先，从存储器读取数据并存储到第一临时存储器。 同时，与来自存储器的数据对应的期望数据从测试器写入第二临时存储器。 此后，将第一临时存储器中的数据和第二临时存储器中的预期数据彼此进行比较，以判断存储器是否具有足够的操作窗口。
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