公开(公告)号：US06285235B1

公开(公告)日：2001-09-04

申请号：US09266774

申请日：1999-03-12

申请人： Kosaku Ichikawa ,  Tateo Koyama ,  Hitoshi Matsumura ,  Shinji Sato

发明人： Kosaku Ichikawa ,  Tateo Koyama ,  Hitoshi Matsumura ,  Shinji Sato

IPC分类号： H03K1704

CPC分类号： H03K17/0406 ,  H02M1/08 ,  H02M1/38 ,  H03K17/04123

摘要： A gate control circuit for turning on and off an insulated gate semiconductor device having gate, emitter and collector terminals, including a first DC power source coupled to the gate terminal via a first switch and configured to apply a positive voltage to the gate terminal in order to turn on the insulated gate semiconductor device when the first switch is turned on and the second switch is turned off; a second DC power source coupled to the gate terminal via a second switch and configured to apply a negative voltage to the gate terminal in order to turn off the insulated gate semiconductor device when the second switch is turned on and the first switch is turned off; a parallel circuit of a diode and a capacitor coupled in series to the second switch; and a turn off assist circuit configured to produce a negative charge on the capacitor to assist in turning off the insulated gate semiconductor device. In a power converter circuit having a plurality of insulated gate semiconductor devices, equalization of delay times for turning off the insulated gate semiconductor devices is achieved by controlling a charged stored in the capacitor of each gate control circuit based on detected collector-emitter voltages or detected emitter currents.

摘要翻译： 一种用于接通和断开具有栅极，发射极和集电极端子的绝缘栅极半导体器件的栅极控制电路，包括经由第一开关耦合到栅极端子的第一DC电源，并且被配置为按顺序向栅极端子施加正电压 当所述第一开关接通并且所述第二开关断开时，接通所述绝缘栅极半导体器件; 第二直流电源，经由第二开关耦合到所述栅极端子，并且被配置为向所述栅极端子施加负电压，以在所述第二开关导通并且所述第一开关断开时关闭所述绝缘栅极半导体器件; 耦合到第二开关的二极管和电容器的并联电路; 以及关闭辅助电路，其被配置为在所述电容器上产生负电荷以帮助关闭所述绝缘栅极半导体器件。 在具有多个绝缘栅极半导体器件的功率转换器电路中，通过基于检测到的集电极 - 发射极电压控制存储在每个栅极控制电路的电容器中的电荷来实现用于关断绝缘栅极半导体器件的延迟时间的均衡 发射极电流。

公开(公告)号：US5948292A

公开(公告)日：1999-09-07

申请号：US16308

申请日：1998-01-30

申请人： Hisao Tanaka ,  Akaru Usui ,  Shinji Sato ,  Hirokazu Miyagawa

发明人： Hisao Tanaka ,  Akaru Usui ,  Shinji Sato ,  Hirokazu Miyagawa

IPC分类号： B23K26/02 ,  B23K26/08 ,  B23K26/14 ,  B23K26/42

CPC分类号： B23K26/046 ,  B23K26/037 ,  B23K26/064 ,  B23K26/0846 ,  B23K26/14 ,  B23K26/1476 ,  B23K26/702

摘要： The laser machining apparatus according to the present invention holds a plate-formed work W giving tension thereto, and comprises a driver base/a work base driving the work in the axial direction, a converging lens for a laser beam L, a laser machining head moving in a direction in which the laser beam L is focused onto the work, an upper work holding member having a nozzle for laser beam irradiation integrated thereto, a bellows for relatively and displaceably connecting the laser machining head and the upper work holding member in the focusing direction, and a lower fixed base/a highly slippery plate located and fixed at a position corresponding to a center of the nozzle, and the work is held between the upper work holding member and the lower fixed base/a highly slippery plate at a position adjacent to the laser beam machining position.

摘要翻译： 根据本发明的激光加工装置保持对其施加张力的板状工件W，并且包括驱动基座/在轴向上驱动工件的工作台，用于激光束L的会聚透镜，激光加工头 在激光束L聚焦到工件上的方向上移动，具有一体化激光束照射用喷嘴的上部工件保持部件，用于将激光加工头和上部工件保持部件相对且可移动地连接的波纹管 聚焦方向，以及位于并固定在与喷嘴的中心对应的位置的下固定底座/高滑板，并且工件被保持在上工件保持构件和下固定底座/高度光滑的板之间 位置与激光束加工位置相邻。

公开(公告)号：US5578756A

公开(公告)日：1996-11-26

申请号：US424001

申请日：1995-04-18

申请人： Yutaka Nakamura ,  Muneyuki Tamogami ,  Shinji Sato ,  Mitsuhiro Tachibana

发明人： Yutaka Nakamura ,  Muneyuki Tamogami ,  Shinji Sato ,  Mitsuhiro Tachibana

IPC分类号： G01M99/00 ,  G01H1/00 ,  G01H17/00 ,  G01M7/00 ,  G01M7/02

CPC分类号： G01M7/00 ,  G01H1/00

摘要： The soundness of a block-shaped structure is evaluated by disposing one set of at least two three-way sensors on a structure, measuring microtremors, determining the contribution factor of rocking vibration, which occupies part of overall vibration, based upon the results of microtremor measurement, and determining extent of rocking vibration at an arbitrary position of the block-shaped structure based upon the contribution factor. Rocking vibration becomes more prevalent as the state of support afforded by the block-shaped structure becomes more unstable. Accordingly, if rocking vibration becomes dominant and exceeds unity, this fact can be used to evaluate the soundness of the block-shaped structure to collapse.

摘要翻译： 通过在结构上设置一组至少两个三路传感器来测量块状结构的健壮性，基于微型摩擦的结果，测量微量元素，确定占据整体振动的一部分的摇摆振动的贡献因子 基于贡献因子测量并确定块状结构的任意位置处的摇摆振动的程度。 由于块状结构的支撑状态变得更加不稳定，摇摆振动变得更加普遍。 因此，如果摇摆振动成为主导且超过一致，则可以使用该事实来评价块状结构的坍塌性。

公开(公告)号：US5229229A

公开(公告)日：1993-07-20

申请号：US689340

申请日：1991-04-23

申请人： Shinji Sato ,  Kenichi Sekimoto ,  Katsuya Shibata ,  Toru Seita

发明人： Shinji Sato ,  Kenichi Sekimoto ,  Katsuya Shibata ,  Toru Seita

IPC分类号： G03F1/62

CPC分类号： G03F1/62 ,  Y10T428/3154 ,  Y10T428/31544 ,  Y10T428/31935 ,  Y10T428/31942

摘要： A pellicle having a reflection-preventing function comprised of a transparent polyvinyl acetal film and a reflection-preventing film formed on at least one surface of the polyvinyl acetal film. The reflection-preventing film is made of a copolymer of a perfluoroalkyl acrylate or methacrylate with a hydroxyalkyl acrylate or methacrylate having (i) a hydroxyalkyl group having 2-3 OH groups on the terminal or side chain and 3-5 carbon atoms, (ii) a hydroxyalkyl group having an OH group on the terminal or side chain and 2-4 carbon atoms, or (iii) a fluorine-containing hydroxyalkyl group having an OH group on the terminal or side chain and 4-12 carbon atoms.

摘要翻译： 一种具有抗反射功能的防护薄膜组件，其由聚乙烯醇缩醛膜的至少一个表面上形成的透明聚乙烯醇缩醛膜和防反射膜构成。 防反射膜由丙烯酸全氟烷基酯或甲基丙烯酸全氟烷基酯与丙烯酸羟烷基酯或（甲基）丙烯酸羟烷基酯的共聚物制成，（i）末端或侧链具有2-3个OH基团的羟基烷基和3-5个碳原子，（ii） ）在末端或侧链具有2-4个碳原子上具有OH基团的羟基烷基，或（iii）末端或侧链具有4-12个碳原子上具有OH基团的含氟羟基烷基。

公开(公告)号：US5001619A

公开(公告)日：1991-03-19

申请号：US526689

申请日：1990-05-22

申请人： Kihei Nakajima ,  Shinji Sato

发明人： Kihei Nakajima ,  Shinji Sato

IPC分类号： H02M7/48 ,  H02M7/527

CPC分类号： H02M7/527

摘要： In an apparatus for carrying out PWM control of an inverter having a filter connected to the a.c. output side thereof, pulse patterns adapted for determining switching timings for canceling a specified harmonic component, e.g., the fifth order harmonic component included in a voltage on the output side of the filter without exerting an influence on the output voltage fundamental wave, are stored in advance into a memory with respect to various vector quantities of the specified harmonic component to select, from a plurality of pulse patterns stored in the memory, each time a pulse pattern for reducing the specified harmonic component. The inverter is subjected to PWM control in accordance with the pulse pattern thus selected.

公开(公告)号：US4816887A

公开(公告)日：1989-03-28

申请号：US008042

申请日：1987-01-21

申请人： Shinji Sato

发明人： Shinji Sato

IPC分类号： H01L21/82 ,  H01L27/118 ,  H01L29/78 ,  H01L27/04

CPC分类号： H01L27/11807

摘要： A masterslice semiconductor device comprised of basic cells having additional transistors formed adjacent to the longitudinal end of one or more pairs of transistors which have a configuration almost the same as in the ordinary basic cell. The basic cells are arranged along columns of the semiconductor substrate they are formed in, and constitute a plurality of basic cell arrays. Each of the additional transistors occupies an individual conduction region for the source and drain and is provided with an individual gate electrode which extends to be in line with or perpendicularly to the extension line of the gate of the transistor pair. The additional transistors occupy the space between adjacent basic cell arrays which are, in the prior art masterslice semiconductor device, exclusively used for distributing wiring lines, and accordingly the width of the space is decreased. Because of the versatility of the additional transistors, and the reduced distance between adjacent basic cell arrays, a unit cell can be organized by using the basic cells belonging to adjacent basic cell arrays. The additional transistors are made inactive when the region which they occupy must be exclusively used for distributing interconnecting lines.

摘要翻译： 一种主板半导体器件，包括具有与一个或多对晶体管的纵向端相邻的附加晶体管的基本单元，其具有与普通基本单元几乎相同的配置。 基本单元沿它们形成的半导体衬底的列排列并且构成多个基本单元阵列。 每个附加晶体管占据用于源极和漏极的单个导电区域，并且设置有单独的栅电极，其延伸成与晶体管对的栅极的延伸线成直线或垂直。 附加晶体管占据了现有技术的主控半导体器件中专用于分配布线的相邻基本单元阵列之间的空间，因此减小了空间的宽度。 由于附加晶体管的通用性以及相邻基本单元阵列之间的距离减小，可以通过使用属于相邻基本单元阵列的基本单元来组织单位单元。 当它们占据的区域必须专门用于分配互连线路时，附加晶体管被制成不活动的。

公开(公告)号：US4668972A

公开(公告)日：1987-05-26

申请号：US643705

申请日：1984-08-24

申请人： Shinji Sato ,  Gensuke Goto

发明人： Shinji Sato ,  Gensuke Goto

IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L27/118

CPC分类号： H01L21/82 ,  H01L27/11807 ,  Y10S257/923

摘要： A masterslice semiconductor device is provided, which reduces or eliminates unused transistors. In the basic cells of the masterslice semiconductor device, each transistor is formed as electrically independent from the others; i.e., each transistor has an individual gate electrode and has an individual region for the source and drain. Terminals formed in parallel to the gate channel of each transistor permits interconnection of the electrodes in a basic cell array using a straight wiring pattern. Such a straight interconnection reduces the effective number of wiring channels needed for a unit cell, and facilitates construction of a larger scale unit cell in a basic cell array.

摘要翻译： 提供了一种减少或消除未使用的晶体管的主板半导体器件。 在主机半导体器件的基本单元中，每个晶体管形成为与电极独立的晶体管; 即，每个晶体管具有单独的栅电极，并且具有用于源极和漏极的单独区域。 与每个晶体管的栅极通道并联形成的端子允许使用直线布线图案的基本单元阵列中的电极互连。 这样的直接互连降低了单元电池所需的布线通道的有效数量，并且有助于在基本单元阵列中构建更大规模的单元电池。

公开(公告)号：US08804430B2

公开(公告)日：2014-08-12

申请号：US13430494

申请日：2012-03-26

申请人： Chun-Hung Lai ,  Shinji Sato ,  Shih-Chung Lee ,  Gerrit Jan Hemink

发明人： Chun-Hung Lai ,  Shinji Sato ,  Shih-Chung Lee ,  Gerrit Jan Hemink

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/1202

摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The voltage applied to a common source line may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction, which may prevent or reduce program disturb. The voltage applied to bit lines of unselected NAND strings may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction.

摘要翻译： 公开了用于操作非易失性存储器的方法和装置。 一个或多个编程条件取决于为编程选择的字线的位置。 应用所选字线相关程序条件可能会减少或消除程序干扰。 施加到公共源极线的电压可以取决于被选择用于编程的字线的位置。 这可以防止或减少穿通传导，这可以防止或减少程序干扰。 施加到未选择NAND串的位线的电压可能取决于选择用于编程的字线的位置。 这可以防止或减少穿透传导。

公开(公告)号：US08773902B2

公开(公告)日：2014-07-08

申请号：US13467289

申请日：2012-05-09

申请人： Deepanshu Dutta ,  Shinji Sato ,  Fumiko Yano

发明人： Deepanshu Dutta ,  Shinji Sato ,  Fumiko Yano

IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427

摘要： In a non-volatile storage system, a programming portion of a program-verify iteration has multiple programming pulses, and storage elements along a word line are selected for programming according to a pattern. Unselected storage elements are grouped to benefit from channel-to-channel capacitive coupling from both primary and secondary neighbor storage elements. The coupling is helpful to boost channel regions of the unselected storage elements to a higher channel potential to prevent program disturb. Each selected storage element has a different relative position within its set. For example, during a first programming pulse, first, second and third storage elements are selected in first, second and third sets, respectively. During a second programming pulse, second, third and first storage elements are selected in the first, second and third sets, respectively. During a third programming pulse, third, first and second storage elements are selected in the first, second and third sets, respectively.

摘要翻译： 在非易失性存储系统中，程序验证迭代的编程部分具有多个编程脉冲，并且根据模式选择沿字线的存储元件进行编程。 未选择的存储元件被分组以从主要和次要邻居存储元件的通道到通道的电容耦合受益。 耦合有助于将未选择的存储元件的通道区域升高到更高的通道电位，以防止程序干扰。 每个选定的存储元件在其集合内具有不同的相对位置。 例如，在第一编程脉冲期间，分别在第一，第二和第三组中选择第一，第二和第三存储元件。 在第二编程脉冲期间，分别在第一，第二和第三组中选择第二，第三和第一存储元件。 在第三编程脉冲期间，分别在第一，第二和第三组中选择第三，第一和第二存储元件。

公开(公告)号：US08503853B2

公开(公告)日：2013-08-06

申请号：US13260624

申请日：2010-03-17

申请人： Hironobu Maeda ,  Keiichi Maeshima ,  Shinji Sato ,  Yoshiyuki Kiriyama ,  Hidekazu Kunieda

发明人： Hironobu Maeda ,  Keiichi Maeshima ,  Shinji Sato ,  Yoshiyuki Kiriyama ,  Hidekazu Kunieda

IPC分类号： G02B6/00

CPC分类号： C08F214/265 ,  C08F214/26 ,  G02B6/02033

摘要： A plastic optical fiber comprising a core and a cladding, wherein the cladding comprises at least one layer, and the cladding comprises a copolymer which comprises 10 to 35% by weight of ethylene, 45 to 69% by weight of tetrafluoroethylene, 20 to 45% by weight of hexafluoropropylene, and 0.01 to 10% by weight of a fluorovinyl compound represented by Formula (1): CH2═CX1(CF2)nX2 (wherein X1 represents a fluorine atom or a hydrogen atom, X2 represents a fluorine atom, a hydrogen atom, or a hydrocarbon group, and n represents an integer from 1 to 10) as a copolymer component.

摘要翻译： 一种包括芯和包层的塑料光纤，其中所述包层包括至少一层，并且所述包层包含共聚物，其包含10至35重量％的乙烯，45至69重量％的四氟乙烯，20至45重量％ 的六氟丙烯和0.01〜10重量％的由式（1）表示的氟乙烯基化合物：CH 2 = CX 1（CF 2）n X 2（其中，X 1表示氟原子或氢原子，X 2表示氟原子，氢 原子或烃基，n表示1〜10的整数）作为共聚物成分。