公开(公告)号：US20130069134A1

公开(公告)日：2013-03-21

申请号：US13608436

申请日：2012-09-10

申请人： Tetsufumi TANAMOTO ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

发明人： Tetsufumi TANAMOTO ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

IPC分类号： H01L27/11

CPC分类号： H01L29/42332 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1104 ,  H01L29/7881

摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.

摘要翻译： 在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极， 第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。 在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜 ，第四浮栅，第六绝缘膜和第二控制栅极。

公开(公告)号：US08243498B2

公开(公告)日：2012-08-14

申请号：US12884452

申请日：2010-09-17

申请人： Keiko Abe ,  Shinobu Fujita

发明人： Keiko Abe ,  Shinobu Fujita

IPC分类号： G11C11/00

CPC分类号： G11C14/009 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/21 ,  G11C14/0054 ,  G11C14/0081

摘要： According to one embodiment, a semiconductor integrated circuit includes first and second inverters, a first transistor which has a gate connected to a word line, a source connected to a first bit line, and a drain connected to an input terminal of the second inverter, a second transistor which has a gate connected to the word line, a source connected to a second bit line, and a drain connected to an input terminal of the first inverter, a first variable resistive element which has a first terminal connected to the drain of the first transistor, and a second terminal connected to an output terminal of the first inverter, and a second variable resistive element which has a first terminal connected to the drain of the second transistor, and a second terminal connected to an output terminal of the second inverter.

摘要翻译： 根据一个实施例，半导体集成电路包括第一和第二反相器，具有连接到字线的栅极的第一晶体管，连接到第一位线的源极和连接到第二反相器的输入端子的漏极， 第二晶体管，其具有连接到字线的栅极，连接到第二位线的源极和连接到第一反相器的输入端子的漏极;第一可变电阻元件，其具有连接到第一位线的漏极的第一端子 第一晶体管和连接到第一反相器的输出端的第二端子，以及第二可变电阻元件，其具有连接到第二晶体管的漏极的第一端子，以及连接到第二晶体管的输出端子的第二端子 逆变器。

公开(公告)号：US07917560B2

公开(公告)日：2011-03-29

申请号：US11635590

申请日：2006-12-08

申请人： Mari Matsumoto ,  Tetsufumi Tanamoto ,  Shinobu Fujita

发明人： Mari Matsumoto ,  Tetsufumi Tanamoto ,  Shinobu Fujita

IPC分类号： G06F1/02

CPC分类号： G06F7/58 ,  G06F17/15

摘要： The random number test circuit includes a shift register which operates based on a clock and which successively stores serial random numbers generated by a random number generation element, a first random number being output from a predetermined stage of the shift register; a comparison circuit which compares the first random number with a second random number located at a distance of a first predetermined number of bits from the first random number, the second random number being generated by the random number generation element; a counter which counts a frequency of occurrence of equality or inequality between the first random number and the second random number, with respect to all bits in the serial random numbers, and a decision circuit which judges an article quality to be good if a count value in the counter indicates a frequency of occurrence equal to or less than a number determined previously by correlation.

摘要翻译： 该随机数测试电路包括一个移位寄存器，该移位寄存器基于时钟进行操作，并连续地存储由随机数生成元件生成的串行随机数，第一随机数从移位寄存器的预定级输出; 比较电路，其将所述第一随机数与位于距所述第一随机数的第一预定位数的距离的第二随机数进行比较，所述第二随机数由所述随机数生成元生成; 相对于串行随机数中的所有比特来计算第一随机数和第二随机数之间的相等或不等式的发生频率的计数器，以及判断电路，如果计数值 在计数器中表示发生的频率等于或小于先前通过相关性确定的数字。

公开(公告)号：US07558813B2

公开(公告)日：2009-07-07

申请号：US12143104

申请日：2008-06-20

申请人： Tetsufumi Tanamoto ,  Shinobu Fujita

发明人： Tetsufumi Tanamoto ,  Shinobu Fujita

IPC分类号： G06F7/58 ,  H01L29/772

CPC分类号： B82Y10/00 ,  G06F7/588 ,  H01L29/7888 ,  H04L9/0861

摘要： The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

公开(公告)号：US20090157780A1

公开(公告)日：2009-06-18

申请号：US12122503

申请日：2008-05-16

申请人： Shinichi YASUDA ,  Shinobu Fujita

发明人： Shinichi YASUDA ,  Shinobu Fujita

IPC分类号： G06F1/02

CPC分类号： G06F7/58

摘要： A random number generating circuit receives as input a first digital random number signal generated at a first generating rate and produces as output a second digital random number signal having a second generating rate that is twice as high as the first generating rate. A semiconductor integrated circuit, an IC card and an information terminal device comprising the random number circuit is provided.

摘要翻译： 随机数产生电路接收以第一产生速率产生的第一数字随机数信号作为输出，产生第二数字随机数信号，该第二数字随机数信号的第二发生速率是第一发生速率的两倍。 提供了包括随机数电路的半导体集成电路，IC卡和信息终端装置。

公开(公告)号：US20080211540A1

公开(公告)日：2008-09-04

申请号：US12038807

申请日：2008-02-27

申请人： Shinobu Fujita

发明人： Shinobu Fujita

IPC分类号： H03K19/173

CPC分类号： H03K19/17748 ,  H03K19/1776 ,  H03K19/1778

摘要： According to some embodiments, an “excess-current programming method” on ZnCdS memory devices for FPGA applications is disclosed. an “excess-current programming method” can also be employed within a variety of other applications, including other memory devices having low On-resistance, such as, e.g., metal-oxide memory like Ti-oxide, Ni-oxide, W-oxide, Cu-oxide and so on. Embodiments of ZnCdS based devices (e.g., memory devices), FPGA elements incorporating the same and methods thereof for reconfigurable circuits can reduce area overhead, power overhead and/or latency (e.g., of FPGA), address a disturbance problem during logic operation, decrease an ON-resistance characteristic and/or obtain increased data retention.

摘要翻译： 根据一些实施例，公开了用于FPGA应用的ZnCdS存储器件上的“过电流编程方法”。 也可以在各种其他应用中使用“过电流编程方法”，包括具有低导通电阻的其它存储器件，例如诸如氧化钛，氧化镍，氧化钼的金属氧化物存储器 ，氧化铜等。 基于ZnCdS的器件（例如，存储器件），与其组合的FPGA元件及其可重构电路的方法的实施例可以减少面积开销，功率开销和/或等待时间（例如FPGA），解决逻辑运算期间的干扰问题，减少 导通电阻特性和/或获得增加的数据保留。

公开(公告)号：US20070296025A1

公开(公告)日：2007-12-27

申请号：US11743265

申请日：2007-05-02

申请人： Mari Matsumoto ,  Ryuji Ohba ,  Shinobu Fujita

发明人： Mari Matsumoto ,  Ryuji Ohba ,  Shinobu Fujita

IPC分类号： H01L29/792

CPC分类号： G06F7/588 ,  H03B29/00

摘要： A random number generating device includes a semiconductor device including a source region, a drain region, a channel region provided between the source region and the drain region, and an insulating portion provided on the channel region, the insulating portion including a trap insulating film having traps based on dangling bonds and expressed by Six(SiO2)y(Si3N4)1-yMz (M is an element other than Si, O, and N, x≧0, 1≧y≧0, z≧0, the case where x=0 and y=1 and z=0 is excluded), conductivity of the channel region varying randomly depending on the amount of charge caught in the traps, and a random number generating unit connected to the semiconductor device and generating random numbers based on a random variation in the conductivity of the channel region.

摘要翻译： 随机数发生装置包括：半导体器件，包括源区域，漏极区域，设置在源极区域和漏极区域之间的沟道区域;以及绝缘部分，设置在沟道区域上，绝缘部分包括捕获绝缘膜， 基于悬挂键并由Si x Si（SiO 2）y（Si 3 N）3表示的陷阱 （M是除Si，O和N之外的元素，x> = 0,1，= y> = 0，z> = 0，x = 0且y = 1，z = 0的情况除外），根据陷阱中捕获的电荷量随机地变化的信道区域的导电率和连接的随机数发生单元 并且基于沟道区域的导电性的随机变化产生随机数。

公开(公告)号：US07111029B2

公开(公告)日：2006-09-19

申请号：US10235827

申请日：2002-09-06

申请人： Shinobu Fujita ,  Ken Uchida ,  Ryuji Ohba ,  Junji Koga

发明人： Shinobu Fujita ,  Ken Uchida ,  Ryuji Ohba ,  Junji Koga

IPC分类号： G06F1/02

CPC分类号： H04L9/0861 ,  G06F7/588

摘要： A random number generating circuit can generate random numbers with high randomness, and can be made as a compact integrated circuit. The random number generating circuit includes an uncertain logic circuit having a flip-flop type logic circuit that gives digital output values not determined definitely by a digital input value, and an equalizing circuit having an exclusive OR operating circuit for equalizing appearance frequencies of “0” and “1” in the digital output values output from the uncertain logic circuit.

公开(公告)号：US07001787B2

公开(公告)日：2006-02-21

申请号：US10902301

申请日：2004-07-30

申请人： Tetsufumi Tanamoto ,  Satoshi Saito ,  Shinobu Fujita

发明人： Tetsufumi Tanamoto ,  Satoshi Saito ,  Shinobu Fujita

IPC分类号： H01L21/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  G11C13/025 ,  H01J9/025 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  Y10T428/256 ,  Y10T428/259

摘要： An electrode manufacturing method comprises: forming plural protruding portions on a surface of a substrate; introducing first particles having a size that changes according to heat, light, or a first solvent between said plural protruding portions; changing the size of the first particles by applying heat, light, or the first solvent to said first particles; and depositing an electrode material onto the surface of said substrate.

摘要翻译： 电极制造方法包括：在基板的表面上形成多个突出部分; 在所述多个突出部之间引入具有根据热，光或第一溶剂变化的尺寸的第一颗粒; 通过向所述第一颗粒施加热，光或第一溶剂来改变第一颗粒的尺寸; 以及将电极材料沉积到所述衬底的表面上。

公开(公告)号：US09003128B2

公开(公告)日：2015-04-07

申请号：US13234837

申请日：2011-09-16

申请人： Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

发明人： Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0897 ,  G06F12/123 ,  G06F2212/225 ,  Y02D10/13

摘要： According to an embodiment, in a cache system, the sequence storage stores sequence data in association with each piece of data to be stored in the volatile cache memory in accordance with the number of pieces of data stored in the nonvolatile cache memory that have been unused for a longer period of time than the data stored in the volatile cache memory or the number of pieces of data stored in the nonvolatile cache memory that have been unused for a shorter period of time than the data stored in the volatile cache memory. The controller causes the first piece of data to be stored in the nonvolatile cache memory in a case where it can be determined that the first piece of data has been unused for a shorter period of time than any piece of the data stored in the nonvolatile cache memory.

摘要翻译： 根据实施例，在高速缓存系统中，序列存储器根据存储在非易失性高速缓冲存储器中的数据的数量与已经被使用的非易失性高速缓冲存储器中存储的数据数量相关联地存储与要存储在易失性高速缓存存储器中的每条数据相关联 比存储在易失性高速缓冲存储器中的数据或存储在非易失性高速缓冲存储器中的数据的时间长于存储在易失性高速缓冲存储器中的数据的时间长于较短时间段的更长时间段。 在可以确定第一条数据已被使用的时间短于存储在非易失性高速缓冲存储器中的任何数据的时间段的情况下，控制器使得第一条数据被存储在非易失性高速缓冲存储器中 记忆。