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262 条记录 (耗时 0.027 秒)

    Carriage system
    52.
    发明申请
    Carriage system 有权
    运输系统

    公开(公告)号：US20060182553A1

    公开(公告)日：2006-08-17

    申请号：US11319733

    申请日：2005-12-29

    申请人： Makoto Yamamoto ,  Kenji Hoshino

    发明人： Makoto Yamamoto ,  Kenji Hoshino

    IPC分类号： B65G1/00

    CPC分类号： B65G47/52 ,  B65G47/5104 ,  B65G47/61 ,  B65G2201/0297 ,  Y10S414/14

    摘要： A running rail 9 and a second overhead vehicle 12 are arranged parallel to a running rail 7 for a first overhead vehicle 10 and closer to inspection devices 20 than the running rail 7. A buffer 14 is provided below the running rail 7. The overhead vehicle 12 conveys a cassette 40 between load ports 24 and the buffer 14. The overhead vehicle 10 conveys the cassette 40 between the buffer 14 and other positions. The present invention can deal with inspection devices or the like which have a high throughput by locally improving their conveying capability.

    摘要翻译： 运行轨道9和第二架空车辆12平行于用于第一架空车辆10的行驶轨道7并且比运行轨道7更靠近检查装置20布置。缓冲器14设置在运行轨道7的下方。 架空车辆12在装载口24和缓冲器14之间传送盒40。 架空车辆10在缓冲器14和其他位置之间传送盒40。 本发明可以通过局部改善其输送能力来处理具有高产量的检查装置等。

    BTL amplifier
    53.
    发明申请
    BTL amplifier 有权
    BTL放大器

    公开(公告)号：US20060097785A1

    公开(公告)日：2006-05-11

    申请号：US11267256

    申请日：2005-11-07

    申请人： Makoto Yamamoto ,  Keiichi Fujii

    发明人： Makoto Yamamoto ,  Keiichi Fujii

    IPC分类号： H03F3/217

    CPC分类号： H03F3/3061

    摘要： In a BTL amplifier of the present invention, between first and third transistor parts (10, 11) which are laterally adjacent, directions of semiconductor regions (102, 104, 106) are parallel. Between the first and second transistor parts (10, 12) and the third and fourth transistor parts (12, 13), each which are longitudinally adjacent, directions of semiconductor regions (102, 104, 106) are perpendicular. The first and the third transistor parts (10, 12) are connected to a power supply terminal (1) through a first wire (51). The second and the fourth transistor parts (11, 13) are connected to a ground terminal (2) through a second wire (52). The first and the second transistor parts (10, 11) are connected to a first output terminal (3) through a third wire (53). The third and the fourth transistor parts (12, 13) are connected to a second output terminal (4) through a fourth wire (54).

    摘要翻译： 在本发明的BTL放大器中，在横向相邻的第一和第三晶体管部分（10,11）之间，半导体区域（102,104,106）的方向是平行的。 在第一和第二晶体管部分（10,12）和第三和第四晶体管部分（12,13）之间，每个半导体区域（102,104,106）的纵向方向相互垂直。 第一和第三晶体管部分（10,12）通过第一线（51）连接到电源端子（1）。 第二和第四晶体管部分（11,13）通过第二线（52）连接到接地端子（2）。 第一和第二晶体管部分（10,11）通过第三导线（53）连接到第一输出端子（3）。 第三和第四晶体管部分（12,13）通过第四线（54）连接到第二输出端子（4）。

    Image generation apparatus, image generation method, game machine using the method, and medium
    56.
    发明授权
    Image generation apparatus, image generation method, game machine using the method, and medium 失效
    图像生成装置，图像生成方法，使用该方法的游戏机以及媒体

    公开(公告)号：US06320582B1

    公开(公告)日：2001-11-20

    申请号：US08875852

    申请日：1997-12-04

    申请人： Makoto Yamamoto ,  Kenji Toma

    发明人： Makoto Yamamoto ,  Kenji Toma

    IPC分类号： G06T1520

    CPC分类号： A63F13/5258 ,  A63F13/10 ,  A63F13/837 ,  A63F2300/306 ,  A63F2300/64 ,  A63F2300/6661 ,  A63F2300/6684 ,  A63F2300/8076 ,  G06T15/10 ,  G06T15/20 ,  G06T17/00

    摘要： In a conventional shooting game machine, it lacked the versatility and appeal of a screen due to the movements of the viewpoint and enemies on the screen being uniform. The present invention comprises an image generating means, which selects one from a plurality of enemies moving within the game space and generates images of this enemy captured from a viewpoint within an imaginary three-dimensional space, an image generating means which implements the processing of attacking the enemies according to the operation of a gun unit, and a viewpoint moving processing means which, together with making said viewpoint follow the enemy, detects the situation of said enemy and implements the controlling of the viewpoint movement.

    摘要翻译： 在传统的射击游戏机中，由于屏幕上的视点和敌人的移动是均匀的，它缺乏屏幕的通用性和吸引力。本发明包括一种图像产生装置，其从多个在其中移动的敌人中选择一个 游戏空间，并生成从虚拟三维空间内的视点拍摄的该敌人的图像，根据枪单元的动作进行攻击敌人的处理的图像生成单元，以及视点移动处理单元， 连同这个观点跟随敌人，侦察敌人的情况，实施观点运动的控制。

    Multiplication circuit
    59.
    发明授权
    Multiplication circuit 失效
    乘法电路

    公开(公告)号：US5835387A

    公开(公告)日：1998-11-10

    申请号：US791022

    申请日：1997-01-27

    申请人： Gouliang Shou ,  Kazunori Motohashi ,  Sunao Takatori ,  Makoto Yamamoto

    发明人： Gouliang Shou ,  Kazunori Motohashi ,  Sunao Takatori ,  Makoto Yamamoto

    IPC分类号： G06J1/00

    CPC分类号： G06J1/00

    摘要： Multiplication is performed including accumulation at high speed by a small quantity of hardware. Analog voltage X.sub.i corresponding to each element of the first input data string is input to capacitance switching circuits 10.sub.1 to 10.sub.n through input terminals 1.sub.1 to 1.sub.n. m bit of digital control data A.sub.i corresponding to each element of the second input data string are input to each capacitance switching circuit 10.sub.i, and each bit a.sub.j of the control signal A.sub.j is input to the corresponding multiplexer circuit 6.sub.ij. In the multiplexer circuit 6.sub.ij, the capacitances C.sub.ij corresponding to the value of each bit of the control signal a.sub.j are connected to the input terminal 1.sub.i or the reference charge V.sub.STD. The voltages corresponding to the products of inputted analog voltages X.sub.1 and the control signals A.sub.i are outputted from each capacitance switching circuit 10.sub.j. The output voltages of each capacitance switching circuit 10.sub.i are parallelly inputted to the operational amplifier 3 connected by a feedback capacitance Cf, and the sum of the input voltages is outputted from the operational amplifier 3. On the other hand, in order to provide a multiplication circuit of high calculation speed without deteriorating the calculation accuracy and circuit density, a multiplication circuit according to the present invention has a MOS switch or MOS multiplexer the MOS of which has a gate with width and length so that a time constant defined by the input capacitance and the switch etc. is constant.

    摘要翻译： 执行乘法，包括由少量硬件高速累积。 对应于第一输入数据串的每个元件的模拟电压Xi通过输入端子11至1n输入到电容切换电路101至10n。 对应于第二输入数据串的每个元件的数字控制数据Ai的m位被输入到每个电容切换电路10i，并且控制信号Aj的每个位aj被输入到相应的多路复用器电路6ij。 在复用器电路6ij中，与控制信号aj的每个位的值相对应的电容Cij连接到输入端1i或参考电荷VSTD。 从各电容切换电路10j输出与输入的模拟电压X1的乘积对应的电压和控制信号Ai。 每个电容切换电路10i的输出电压被并行地输入到由反馈电容Cf连接的运算放大器3，并且从运算放大器3输出输入电压的和。另一方面，为了提供乘法 具有高计算速度的电路，而不降低计算精度和电路密度，根据本发明的乘法电路具有MOS开关或MOS多路复用器，其MOS具有宽度和长度的栅极，使得由输入电容定义的时间常数 并且开关等是恒定的。