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69 条记录 (耗时 0.027 秒)

    Wide-range local bias generator for body bias grid
    54.
    发明授权
    Wide-range local bias generator for body bias grid 失效
    用于车身偏置网格的宽范围局部偏置发生器

    公开(公告)号：US06784722B2

    公开(公告)日：2004-08-31

    申请号：US10267951

    申请日：2002-10-09

    申请人： Stephen H. Tang ,  Dinesh Somasekhar ,  James W. Tschanz ,  Vivek K. De

    发明人： Stephen H. Tang ,  Dinesh Somasekhar ,  James W. Tschanz ,  Vivek K. De

    IPC分类号： G35F110

    CPC分类号： G05F3/205 ,  H03K2217/0018

    摘要： A circuit is provided having a differential difference amplifier (DDA) having first and second inputs to receive a desired body bias signal, and a third input to receive a supply voltage, the DDA configured to generate an intermediate output signal, the intermediate output signal coupled to an output buffer generating an output signal having a desired gain, the DDA having a fourth input, to cause the output signal to reference to variations in the supply voltage.

    摘要翻译： 提供一种具有差分差分放大器（DDA）的电路，差分差分放大器（DDA）具有第一和第二输入端以接收所需的体偏置信号;以及第三输入端，用于接收电源电压，所述DDA被配置为产生中间输出信号，所述中间输出信号耦合 到产生具有期望增益的输出信号的输出缓冲器，DDA具有第四输入，以使输出信号参考电源电压的变化。

    Spin transfer torque based memory elements for programmable device arrays
    55.
    发明授权
    Spin transfer torque based memory elements for programmable device arrays 有权
    用于可编程器件阵列的基于转移转矩的存储元件

    公开(公告)号：US09270278B2

    公开(公告)日：2016-02-23

    申请号：US13997962

    申请日：2012-03-30

    申请人： Arijit Raychowdhury ,  James W. Tschanz ,  Vivek De

    发明人： Arijit Raychowdhury ,  James W. Tschanz ,  Vivek De

    IPC分类号： H03K19/177 ,  G11C11/16

    CPC分类号： H03K19/17728 ,  G11C11/16 ,  H03K19/177

    摘要： Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.

    摘要翻译： 这里公开了使用基于高密度旋转转矩（STT）的存储器元件的半导体器件阵列，诸如现场可编程门阵列（FPGA）和复数可编程逻辑阵列（CPLAs）。 基于STT的存储器元件可以是独立的FPGA / CPLAs，或者可以嵌入在微处理器和/或数字信号处理（DSP）片上系统（SoC）中，以提供设计灵活性，以实现低功率，可扩展，安全 和可重构硬件架构。 由于配置存储在FPGA / CPLA裸片本身，所以每次在外部存储器上加载配置的需求都将在设备通电时被消除。 除了即时启动，消除配置I / O流量导致节电和可能的引脚数减少。 通过消除将配置数据存储在外部存储器中的需要，安全性大大提高。

    Multi-supply sequential logic unit
    57.
    发明授权
    Multi-supply sequential logic unit 有权
    多电源顺序逻辑单元

    公开(公告)号：US08901819B2

    公开(公告)日：2014-12-02

    申请号：US13992894

    申请日：2011-12-14

    申请人： Arijit Raychowdhury ,  Jaydeep P. Kulkarni ,  James W. Tschanz

    发明人： Arijit Raychowdhury ,  Jaydeep P. Kulkarni ,  James W. Tschanz

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/017509 ,  G06F1/10 ,  G06F1/3296 ,  Y02D10/172

    摘要： Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.

    摘要翻译： 这里描述了用于减少处理器中的顺序逻辑单元的时钟到输出延迟的装置，方法和系统。 所述装置包括顺序单元，包括：数据路径，用于接收输入信号，包括在第一电源电平上操作的逻辑门，所述数据路径以产生输出信号; 以及时钟路径，包括用于在第二电源电平上操作的逻辑门，所述时钟路径的逻辑门使用采样信号对所述输入信号进行采样以产生所述输出信号，其中所述第二电源电平高于所述第一电力 供应水平。 该装置改善（即减少）顺序单元的建立时间，并允许处理器以最小工作电压（Vmin）运行，而不降低顺序单元的性能。

    SPIN TRANSFER TORQUE BASED MEMORY ELEMENTS FOR PROGRAMMABLE DEVICE ARRAYS
    58.
    发明申请
    SPIN TRANSFER TORQUE BASED MEMORY ELEMENTS FOR PROGRAMMABLE DEVICE ARRAYS 有权
    用于可编程器件阵列的基于转子扭矩的记忆元件

    公开(公告)号：US20140035617A1

    公开(公告)日：2014-02-06

    申请号：US13997962

    申请日：2012-03-30

    申请人： Arijit Raychowdhury ,  James W. Tschanz ,  Vivek De

    发明人： Arijit Raychowdhury ,  James W. Tschanz ,  Vivek De

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17728 ,  G11C11/16 ,  H03K19/177

    摘要： Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.

    摘要翻译： 这里公开了使用基于高密度旋转转矩（STT）的存储器元件的半导体器件阵列，诸如现场可编程门阵列（FPGA）和复数可编程逻辑阵列（CPLAs）。 基于STT的存储器元件可以是独立的FPGA / CPLAs，或者可以嵌入在微处理器和/或数字信号处理（DSP）片上系统（SoC）中，以提供设计灵活性，以实现低功率，可扩展，安全 和可重构硬件架构。 由于配置存储在FPGA / CPLA裸片本身，所以每次在外部存储器上加载配置的需求都将在设备通电时被消除。 除了即时启动，消除配置I / O流量导致节电和可能的引脚数减少。 通过消除将配置数据存储在外部存储器中的需要，安全性大大提高。

    DUAL LOOP DIGITAL LOW DROP REGULATOR AND CURRENT SHARING CONTROL APPARATUS FOR DISTRIBUTABLE VOLTAGE REGULATORS
    59.
    发明申请
    DUAL LOOP DIGITAL LOW DROP REGULATOR AND CURRENT SHARING CONTROL APPARATUS FOR DISTRIBUTABLE VOLTAGE REGULATORS 审中-公开
    双环数字低电平调节器和分布式电压调节器的电流共享控制装置

    公开(公告)号：US20140277812A1

    公开(公告)日：2014-09-18

    申请号：US13801777

    申请日：2013-03-13

    申请人： Yi-Chun Shih ,  Kaushik Mazumdar ,  Stephen T. Kim ,  Rinkle Jain ,  James W. Tschanz ,  Muhammad M. Khellah

    发明人： Yi-Chun Shih ,  Kaushik Mazumdar ,  Stephen T. Kim ,  Rinkle Jain ,  James W. Tschanz ,  Muhammad M. Khellah

    IPC分类号： G05F5/00

    CPC分类号： G05F1/563 ,  G05F1/00 ,  G05F1/46 ,  H02M3/156

    摘要： Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.

    摘要翻译： 描述了一种装置，其包括：耦合到输入电源和负载的多个晶体管; 第一比较器，其具有耦合到所述负载的第一节点，以及耦合到第一参考的第二节点; 第二比较器，其具有耦合到所述负载的第一节点，以及耦合到第二参考的第二节点，所述第二参考与所述第一参考不同; 以及逻辑单元，用于接收第一比较器的输出和第二比较器的输出，逻辑单元根据第一和第二比较器的输出接通或关断多个晶体管的晶体管。