公开(公告)号：US11610909B2

公开(公告)日：2023-03-21

申请号：US16875460

申请日：2020-05-15

Applicant: Sunrise Memory Corporation

Inventor： Eli Harari ,  Wu-Yi Henry Chien

IPC: H01L27/11556 ,  G11C5/06 ,  G11C5/02 ,  H01L27/11582

Abstract: A process forms thin-film storage transistors (e.g., HNOR devices) with improved channel regions by conformally depositing a thin channel layer in a cavity bordering a source region and a drain region, such that a portion of the channel material abuts by junction contact the source region and another portion of the channel layer abut by junction contact the drain region. The cavity is also bordered by a storage layer. In one form of the process, the channel region is formed before the storage layer is formed. In another form of the storage layer is formed before the channel region is formed.

公开(公告)号：US20230081427A1

公开(公告)日：2023-03-16

申请号：US17823455

申请日：2022-08-30

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11592

Abstract: A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent an oxide semiconductor channel region. The ferroelectric storage transistors thus formed are junctionless transistors having no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a common source line and a common bit line, the common source line and the common bit line formed on a first side of the channel region and the ferroelectric gate dielectric layer and in electrical contact with the oxide semiconductor channel region. The ferroelectric storage transistors in a NOR memory string are controlled by individual control gate electrodes formed on a second side, opposite the first side, of the ferroelectric gate dielectric layer.

公开(公告)号：US20230078883A1

公开(公告)日：2023-03-16

申请号：US17823464

申请日：2022-08-30

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Wu-Yi Henry Chien ,  Christopher J. Petti ,  Eli Harari

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/51 ,  H01L29/78 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11597 ,  H01L27/11592 ,  H01L29/66

Abstract: A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent an oxide semiconductor channel region. The ferroelectric storage transistors thus formed are junctionless transistors having no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a common source line and a common bit line that are formed on a first side of the channel region, away from the ferroelectric gate dielectric layer, and in electrical contact with the oxide semiconductor channel region. The ferroelectric storage transistors in a NOR memory string are controlled by individual control gate electrodes that are formed adjacent the ferroelectric gate dielectric layer on a second side, opposite the first side, of the channel region.

公开(公告)号：US20230072345A1

公开(公告)日：2023-03-09

申请号：US18050937

申请日：2022-10-28

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Vinod Purayath ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L27/105 ,  H01L29/66 ,  H01L29/786 ,  H01L21/3065

Abstract: A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f)selectively etching the semiconductor material to remove the doped portion of the semiconductor material without removing the remainder of the semiconductor material.

公开(公告)号：US20220344364A1

公开(公告)日：2022-10-27

申请号：US17714776

申请日：2022-04-06

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Vinod Purayath ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L27/11578

Abstract: Carbon has many advantageous uses as a sacrificial material in the fabricating thin-film storage transistors, such as those organized as NOR memory strings. In one implementation, the carbon layers are replaced by heavily doped n-type polysilicon source and drain regions at a late step during device fabrication. As a result, many high temperature steps within the fabrication process may now be carried out without concern for thermal diffusion from the heavily doped polysilicon, thus allowing phosphorus to be used as the n-type dopant.

公开(公告)号：US20210320182A1

公开(公告)日：2021-10-14

申请号：US17222082

申请日：2021-04-05

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Wu-Yi Henry Chien ,  Scott Brad Herner ,  Eli Harari

IPC: H01L29/423 ,  H01L27/11568 ,  H01L29/786 ,  H01L29/792

Abstract: A thin-film memory transistor includes a source region, a drain region, a channel region, a gate electrode, and a charge-trapping layer provided between the channel region and the gate electrode and electrically isolated therefrom, wherein the charge-trapping layer has includes a number of charge-trapping sites that is 70% occupied or evacuated using a single voltage pulse of a predetermined width of 500 nanoseconds or less and a magnitude of 15.0 volts or less. The charge-trapping layer comprises silicon-rich nitride may have a refractive index of 2.05 or greater or comprises nano-crystals of germanium (Ge), zirconium oxide (ZrO2), or zinc oxide (ZnO). The thin-film memory transistor may be implemented, for example, in a 3-dimensional array of NOR memory strings formed above a planar surface of a semiconductor substrate.

公开(公告)号：US20210193660A1

公开(公告)日：2021-06-24

申请号：US17125477

申请日：2020-12-17

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Vinod Purayath ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L27/105 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/786

Abstract: A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped portion of the semiconductor material without removing the remainder of the semiconductor material.

公开(公告)号：US20200098789A1

公开(公告)日：2020-03-26

申请号：US16578970

申请日：2019-09-23

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Chenming Hu ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L21/02 ,  H01L21/28

Abstract: A thin-film storage transistor includes (a) first and second semiconductor regions comprising polysilicon of a first conductivity; and (b) a channel region between the first and second semiconductor regions, the channel region comprising single-crystal epitaxial grown silicon, and wherein the thin-film storage transistor is formed above a monocrystalline semiconductor substrate.

公开(公告)号：US20200020718A1

公开(公告)日：2020-01-16

申请号：US16510610

申请日：2019-07-12

Applicant: Sunrise Memory Corporation

Inventor： Eli Harari ,  Scott Brad Herner ,  Wu-Yi Henry Chien

IPC: H01L27/11582 ,  H01L21/306 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L29/08 ,  H01L21/027 ,  H01L21/3105

Abstract: A process for manufacturing a 3-dimensional memory structure includes: (a) providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) first and second semiconductor layers of a first conductivity; (ii) a dielectric layer separating the first and second semiconductor layer; and (ii) one or more sacrificial layers, at least one of sacrificial layers being adjacent the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches each separating and exposing sidewalls of adjacent active stacks; (c) filling the first set of trenches by a silicon oxide; (d) patterning and etching the silicon oxide to create silicon oxide columns each abutting adjacent active stacks and to expose portions of one or more sidewalls of the active stacks; (e) removing the sacrificial layers from exposed portions of the sidewalls by isotropic etching through the exposed portions of the sidewalls of the active stacks to create corresponding cavities in the active layers; (f) filling the cavities in the active stacks by a metallic or conductor material; (g) recessing the dielectric layer from the exposed sidewalls of the active stacks; and (h) filling recesses in the dielectric layer by a third semiconductor layer of a second conductivity opposite the first conductivity.

公开(公告)号：US20190206890A1

公开(公告)日：2019-07-04

申请号：US16230981

申请日：2018-12-21

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari ,  Wu-Yi Henry Chien ,  Scott Brad Herner

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/76837 ,  H01L21/76843

Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.