公开(公告)号：US11615227B2

公开(公告)日：2023-03-28

申请号：US17129195

申请日：2020-12-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chia Lai ,  Kuo-Ji Chen ,  Wen-Hao Chen ,  Wun-Jie Lin ,  Yu-Ti Su ,  Rabiul Islam ,  Shu-Yi Ying ,  Stefan Rusu ,  Kuan-Te Li ,  David Barry Scott

IPC分类号： G06F30/30 ,  G06F30/392 ,  H01L27/02 ,  G01R31/50 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398 ,  G06F117/02

摘要： An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

公开(公告)号：US20190148357A1

公开(公告)日：2019-05-16

申请号：US16231764

申请日：2018-12-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wun-Jie Lin ,  Ching-Hsiung Lo ,  Jen-Chou Tseng ,  Han-Jen Yang ,  Arabinda Das

IPC分类号： H01L27/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/45 ,  H01L29/423 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L27/0266 ,  H01L21/823431 ,  H01L27/027 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/785

摘要： A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.

公开(公告)号：US10269986B2

公开(公告)日：2019-04-23

申请号：US15074065

申请日：2016-03-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sun-Jay Chang ,  Ming-Hsiang Song ,  Jen-Chou Tseng ,  Wun-Jie Lin ,  Bo-Ting Chen

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L29/861 ,  H01L29/868

摘要： A diode includes a first plurality of combo fins having lengthwise directions parallel to a first direction, wherein the first plurality of combo fins comprises portions of a first conductivity type. The diodes further includes a second plurality of combo fins having lengthwise directions parallel to the first direction, wherein the second plurality of combo fins includes portions of a second conductivity type opposite the first conductivity type. An isolation region is located between the first plurality of combo fins and the second plurality of combo fins. The first and the second plurality of combo fins form a cathode and an anode of the diode. The diode is configured to have a current flowing in a second direction perpendicular to the first direction, with the current flowing between the anode and the cathode.

公开(公告)号：US20180166437A1

公开(公告)日：2018-06-14

申请号：US15894327

申请日：2018-02-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wun-Jie Lin ,  Ching-Hsiung Lo ,  Jen-Chou Tseng ,  Han-Jen Yang ,  Arabinda Das

IPC分类号： H01L27/02 ,  H01L29/78 ,  H01L29/45 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L29/417

CPC分类号： H01L27/0266 ,  H01L21/823431 ,  H01L27/027 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/785

摘要： A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.

公开(公告)号：US09893052B2

公开(公告)日：2018-02-13

申请号：US15212579

申请日：2016-07-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wun-Jie Lin ,  Ching-Hsiung Lo ,  Jen-Chou Tseng ,  Han-Jen Yang ,  Arabinda Das

IPC分类号： H01L21/02 ,  H01L27/02 ,  H01L27/088 ,  H01L29/45 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08

CPC分类号： H01L27/0266 ,  H01L21/823431 ,  H01L27/027 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/785

摘要： A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.

公开(公告)号：US09812436B2

公开(公告)日：2017-11-07

申请号：US14844272

申请日：2015-09-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Ti Su ,  Wun-Jie Lin ,  Han-Jen Yang ,  Shui-Ming Cheng ,  Ming-Hsiang Song

IPC分类号： H01L29/66 ,  H01L27/02 ,  H01L27/06 ,  H01L29/74 ,  H01L27/08

CPC分类号： H01L27/0248 ,  H01L27/0262 ,  H01L27/0629 ,  H01L27/0647 ,  H01L27/0814 ,  H01L29/7436

摘要： An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

公开(公告)号：US09728531B2

公开(公告)日：2017-08-08

申请号：US15262588

申请日：2016-09-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wun-Jie Lin ,  Han-Jen Yang ,  Yu-Ti Su

IPC分类号： H01L27/02 ,  H01L29/66 ,  H01L21/82 ,  H02H9/04 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L23/60 ,  H01L21/28

CPC分类号： H01L27/0266 ,  H01L21/28123 ,  H01L21/823431 ,  H01L21/823437 ,  H01L23/60 ,  H01L27/0207 ,  H01L27/0292 ,  H01L27/0886 ,  H01L29/1095 ,  H01L29/66545 ,  H02H9/046

摘要： An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, wherein each active region is substantially uniform in length. The first gate device and the second device are formed over a first well having a first conductivity type and the dummy gate is formed over a second well having a second conductivity type.

公开(公告)号：US09559008B2

公开(公告)日：2017-01-31

申请号：US14942306

申请日：2015-11-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wun-Jie Lin ,  Ching-Hsiung Lo ,  Jen-Chou Tseng

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/02 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L27/0248 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0266 ,  H01L27/027 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/42372 ,  H01L29/66636 ,  H01L29/785

摘要： A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of semiconductor fins over the semiconductor strips. A gate stack is disposed over and crossing the plurality of semiconductor fins. A drain epitaxy semiconductor region is disposed on a side of the gate stack and connected to the plurality of semiconductor fins. The drain epitaxy semiconductor region includes a first portion adjoining the semiconductor fins, wherein the first portion forms a continuous region over and aligned to the plurality of semiconductor strips. The drain epitaxy semiconductor region further includes second portions farther away from the gate stack than the first portion. Each of the second portions is over and aligned to one of the semiconductor strips. The second portions are parallel to each other, and are separated from each other by a dielectric material.

摘要翻译： 一种器件包括多个STI区域，在STI区域之间并且彼此平行的多个半导体条以及半导体条上的多个半导体鳍片。 栅极叠层设置在多个半导体鳍片上并与之交叉。 漏极外延半导体区域设置在栅极堆叠的一侧并连接到多个半导体鳍片。 所述漏极外延半导体区域包括邻接所述半导体鳍片的第一部分，其中所述第一部分在所述多个半导体条带之上形成连续区域并且与所述多个半导体条带对准。 漏极外延半导体区域还包括比第一部分更远离栅极堆叠的第二部分。 每个第二部分在其中一个半导体条上方并对齐。 第二部分彼此平行，并且通过电介质材料彼此分离。

公开(公告)号：US09443850B2

公开(公告)日：2016-09-13

申请号：US13932521

申请日：2013-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wun-Jie Lin ,  Jen-Chou Tseng ,  Ming-Hsiang Song

IPC分类号： H01L27/10 ,  H01L21/82 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/28

CPC分类号： H01L27/0886 ,  H01L21/28123 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0266

摘要： An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between two gate devices. The device further includes at least one dummy gate between two epitaxially grown active regions. Each active region is substantially uniform in length.

摘要翻译： 集成电路器件包括生长在衬底上的至少两个外延生长的有源区，该有源区位于两个栅极器件之间。 该器件还包括两个外延生长的有源区之间的至少一个伪栅极。 每个活性区域的长度基本上是均匀的。

公开(公告)号：US09397098B2

公开(公告)日：2016-07-19

申请号：US14555423

申请日：2014-11-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wun-Jie Lin ,  Ching-Hsiung Lo ,  Jen-Chou Tseng ,  Han-Jen Yang ,  Arabinda Das

IPC分类号： H01L21/02 ,  H01L27/088 ,  H01L29/45 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L27/0266 ,  H01L21/823431 ,  H01L27/027 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/785

摘要： A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.

摘要翻译： 半导体器件包括在衬底上的半导体条上的半导体鳍片。 半导体翅片彼此平行。 栅堆叠在半导体鳍上方，并且漏极外延半导体区域从栅堆叠的侧面和半导体条横向设置。 第一电介质层在衬底上，并且第一介电层具有第一金属层。 第二电介质层在第一电介质层之上，第二介电层具有第二金属层。 通孔从第二金属层延伸并穿过第一介电层，并且通孔电耦合到漏极外延半导体区域。